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1. (WO2017034203) OXIDE TRANSISTOR AND MANUFACTURING METHOD THEREFOR
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Pub. No.: WO/2017/034203 International Application No.: PCT/KR2016/009000
Publication Date: 02.03.2017 International Filing Date: 17.08.2016
IPC:
H01L 29/786 (2006.01) ,H01L 21/324 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
324
Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Applicants:
충북대학교 산학협력단 CHUNGBUK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION [KR/KR]; 충청북도 청주시 서원구 충대로 1 1, Chungdae-ro, Seowon-gu Cheongju-si Chungcheongbuk-do 28644, KR
Inventors:
김성진 KIM, Sung Jin; KR
김원유 KIM, Won You; KR
엄주송 EOM, Ju Song; KR
Agent:
김정현 KIM, Jeong Hyeon; KR
Priority Data:
10-2015-011806721.08.2015KR
Title (EN) OXIDE TRANSISTOR AND MANUFACTURING METHOD THEREFOR
(FR) TRANSISTOR À OXYDE ET SON PROCÉDÉ DE FABRICATION
(KO) 산화물 트랜지스터 및 그 제조 방법
Abstract:
(EN) An oxide transistor and a manufacturing method therefor are disclosed. According to one aspect of the present invention, the oxide transistor comprises: a substrate to be used as a gate electrode; a gate insulator formed on the substrate; an oxide thin film formed by forming an oxide active layer by irradiating predetermined ultraviolet rays for a predetermined time during a step of spin coating, on the upper part of the silicon insulator, a mixture solution of a semiconductor material having a band gap of a predetermined reference value or more, and then annealing the same; and source and drain electrodes formed by depositing aluminum on the upper part of the oxide thin film.
(FR) La présente invention concerne un transistor à oxyde et son procédé de fabrication. Selon un aspect de la présente invention, le transistor à oxyde comprend : un substrat destiné à être utilisé en tant qu'électrode de grille; un isolateur de grille formé sur le substrat; un film mince d'oxyde formé par la formation d'une couche active d'oxyde en exposant à des rayons ultraviolets prédéfinis pendant une durée prédéfinie au cours d'une étape de revêtement par centrifugation la partie supérieure de l'isolateur au silicium, une solution de mélange d'un matériau semi-conducteur ayant une bande interdite supérieure ou égale à une valeur de référence prédéfinie, et en recuisant celui-ci; et des électrodes de source et de drain formées par un dépôt d'aluminium sur la partie supérieure de la couche mince d'oxyde.
(KO) 본 발명은 산화물 트랜지스터 및 그 제조 방법에 대하여 개시한다. 본 발명의 일면에 따른 산화물 트랜지스터는, 게이트 전극으로 사용되는 기판; 상기 기판 상에 형성된 게이트절연막; 상기 실리콘 절연막의 상부에 밴드갭(Gap)이 기설정된 기준치 이상인 반도체 물질의 혼합 용액을 스핀코팅(Spin Coating)하는 공정중에 기설정된 자외선을 기설정된 시간동안 조사하여 산화물 활성층을 형성한 후 어닐링(annealing)함에 따라 형성된 산화물 박막; 및 상기 산화물 박막의 상부에 알루미늄을 증착하여 형성된 소스 및 드레인 전극을 포함하는 것을 특징으로 한다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)