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1. WO2017033939 - SEMICONDUCTOR DEVICE

Publication Number WO/2017/033939
Publication Date 02.03.2017
International Application No. PCT/JP2016/074540
International Filing Date 23.08.2016
IPC
H01L 29/861 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
86controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861Diodes
H01L 29/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02Semiconductor bodies
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/868 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
86controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
861Diodes
868PIN diodes
CPC
H01L 23/29
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
29characterised by the material ; , e.g. carbon
H01L 23/291
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
29characterised by the material ; , e.g. carbon
291Oxides or nitrides or carbides, e.g. ceramics, glass
H01L 23/3171
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3157Partial encapsulation or coating
3171the coating being directly applied to the semiconductor body, e.g. passivation layer
H01L 23/3192
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
28Encapsulations, e.g. encapsulating layers, coatings, ; e.g. for protection
31characterised by the arrangement ; or shape
3157Partial encapsulation or coating
3192Multilayer coating
H01L 29/0661
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0657characterised by the shape of the body
0661specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
H01L 29/2003
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
12characterised by the materials of which they are formed
20including, apart from doping materials or other impurities, only AIIIBV compounds
2003Nitride compounds
Applicants
  • 学校法人法政大学 HOSEI UNIVERSITY [JP]/[JP]
  • 株式会社サイオクス SCIOCS COMPANY LIMITED [JP]/[JP]
  • 住友化学株式会社 SUMITOMO CHEMICAL COMPANY, LIMITED [JP]/[JP]
Inventors
  • 中村 徹 NAKAMURA Tohru
  • 三島 友義 MISHIMA Tomoyoshi
  • 太田 博 OHTA Hiroshi
  • 山本 康博 YAMAMOTO Yasuhiro
  • 堀切 文正 HORIKIRI Fumimasa
Agents
  • 福岡 昌浩 FUKUOKA Masahiro
Priority Data
2015-16719626.08.2015JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体装置
Abstract
(EN)
This semiconductor device is provided with: a semiconductor member that includes a mesa structure in which a first and second semiconductor layer are layered and which has a pn junction; an insulating film that is disposed upon the side surfaces of the mesa and the top surface of the outer sides of the mesa; a first electrode that is connected to the second semiconductor layer on the top surface of the mesa and extends across the mesa side surfaces and the mesa outer side top surfaces upon the insulating film; and a second electrode that is connected to the first semiconductor layer on the bottom surface of the first semiconductor layer. The insulating film is formed by including a first and second insulating layer. The first insulating layer covers the corners connecting the mesa side surfaces and the mesa outer side top surfaces, and the second insulating layer covers the pn junction interfaces on the mesa side surfaces or covers directly below the electrode edges of the first electrode while composing the entire thickness of the insulating film directly below the electrode edges. The relative permittivity of the second insulating layer is equal to or higher than the relative permittivity of the semiconductor member. The relative permittivity of the first insulating layer is lower than the relative permittivity of the second insulating layer.
(FR)
Le dispositif à semi-conducteurs de l’invention possède : un élément semi-conducteur sur lequel sont stratifiées une première ainsi qu’une seconde couche semi-conductrice, et qui contient une structure mesa possédant une liaison pn ; un film isolant disposé sur une face côté mesa et sur une face supérieure non côté mesa ; une première électrode qui est connectée à la seconde couche semi-conductrice sur une face supérieure mesa, et qui se prolonge sur le film isolant, sur la face côté mesa et sur la face supérieure non côté mesa ; et une seconde électrode connectée à la première couche semi-conductrice au niveau d’une face inférieure de celle-ci. Le film isolant est configuré de manière à inclure une première et une seconde couche isolante. La première couche isolante revêt une partie angle de connexion de la face côté mesa et de la face supérieure non côté mesa. La seconde couche isolante revêt une interface de liaison pn de la face côté mesa, ou configure toute l’épaisseur du film isolant directement sous une extrémité de la première électrode et revêt directement le dessous de l’extrémité de de cette électrode. La permittivité relative de la seconde couche isolante est supérieure ou égale à celle de l’élément semi-conducteur, et la permittivité relative de la première couche isolante est inférieure à celle de la seconde couche isolante.
(JA)
半導体装置は、第1、第2半導体層が積層されpn接合を有するメサ構造を含む半導体部材と、メサ側面上およびメサ外側上面上に配置された絶縁膜と、メサ上面で第2半導体層と接続され絶縁膜上でメサ側面上およびメサ外側上面上に延在する第1電極と、第1半導体層の下面で第1半導体層と接続された第2電極と、を有し、絶縁膜は、第1および第2絶縁層を含んで構成され、第1絶縁層は、メサ側面とメサ外側の上面とが接続する角部を覆い、第2絶縁層は、メサ側面のpn接合界面を覆うか、または、第1電極の電極端直下で絶縁膜の全厚さを構成して電極端直下を覆い、第2絶縁層の比誘電率は、半導体部材の比誘電率以上であり、第1絶縁層の比誘電率は、第2絶縁層の比誘電率よりも小さい。
Also published as
Latest bibliographic data on file with the International Bureau