In a time-interleaved Analog to Digital Converter, circuit components and capacitances may be shared among a plurality of sample and hold circuits (16, 36, 18, 38, 20, 40, 22, 42) in each of two sets. The two shared circuits (12, 32, 14, 34) alternate, on different half-periods of a master clock signal (Clk), between charging a capacitance and sampling an input in an overlapping manner such that one is charging while the other is sampling. One sample and hold circuit (16, 36, 18, 38, 20, 40, 22, 42) is activated during each successive half-period (following a charging half-period) by independent, sequential, non-overlapping clocking signals (Clk1-Clk4). To improve SNDR, at least one switch (M11) is bootstrapped by driving its gate terminal with the voltage of a capacitor configured between the gate and the input signal. By sharing at least some components among multiple sample and hold circuits (16, 36, 18, 38, 20, 40, 22, 42), the number of gates driven by clock signals is reduced, reducing clock distribution and calibration complexity, and the circuit area is reduced.