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1. (WO2017032022) DEVICE AND PROCESSING ARCHITECTURE FOR INSTRUCTION MEMORY EFFICIENCY

Pub. No.:    WO/2017/032022    International Application No.:    PCT/CN2016/080512
Publication Date: Fri Mar 03 00:59:59 CET 2017 International Filing Date: Fri Apr 29 01:59:59 CEST 2016
IPC: G06F 9/30
Applicants: HUAWEI TECHNOLOGIES CO., LTD.
Inventors: VINCENT, John Edward.
SINN, Peter Man Kin
WATSON, Benton
Title: DEVICE AND PROCESSING ARCHITECTURE FOR INSTRUCTION MEMORY EFFICIENCY
Abstract:
Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.