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1. (WO2017031966) THIN-FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, ARRAY SUBSTRATE AND DISPLAY PANEL CONTAINING THE SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/031966 International Application No.: PCT/CN2016/074263
Publication Date: 02.03.2017 International Filing Date: 22.02.2016
IPC:
H01L 29/786 (2006.01) ,H01L 21/336 (2006.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No. 10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
LIU, Xiang; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan Chen 10th Floor, Tower D, Minsheng Financial Center 28 Jianguomennei Avenue Dongcheng District, Beijing 100005, CN
Priority Data:
201510524296.124.08.2015CN
Title (EN) THIN-FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, ARRAY SUBSTRATE AND DISPLAY PANEL CONTAINING THE SAME
(FR) TRANSISTOR À COUCHES MINCES, SON PROCÉDÉ DE FABRICATION, SUBSTRAT DE MATRICE ET ÉCRAN D'AFFICHAGE LE CONTENANT
Abstract:
(EN) The present disclosure provides a thin-film transistor (TFT). The TFT includes a gate electrode on a substrate; a gate insulating layer covering the gate electrode; and an active layer having a channel region between a source and drain electrode. The TFT also includes the source and drain electrode on the gate insulating layer; a protection layer on the source and drain electrode; and an opening through the protection layer and the source and drain electrode, the opening exposing the channel region.
(FR) La présente invention concerne un transistor à couches minces (TFT). Le TFT comprend une électrode de grille sur un substrat ; une couche d'isolation de grille couvrant l'électrode de grille ; et une couche active comportant une zone de canal entre des électrodes de source et de drain. Le TFT comprend également les électrodes de source et de drain sur la couche d'isolation de grille ; une couche de protection sur les électrodes de source et de drain ; et une ouverture à travers la couche de protection et les électrodes de source et de drain, l'ouverture faisant apparaître la zone de canal.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)