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1. (WO2017031940) ARRAY SUBSTRATE, FABRICATION METHOD THEREFOR, AND DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/031940 International Application No.: PCT/CN2016/071618
Publication Date: 02.03.2017 International Filing Date: 21.01.2016
IPC:
H01L 21/77 (2017.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
刘威 LIU, Wei; CN
Agent:
北京市柳沈律师事务所 LIU, SHEN & ASSOCIATES; 中国北京市 海淀区彩和坊路10号1号楼10层 10th Floor, Building 1, 10 Caihefang Road, Haidian District Beijing 100080, CN
Priority Data:
201510523842.X24.08.2015CN
Title (EN) ARRAY SUBSTRATE, FABRICATION METHOD THEREFOR, AND DISPLAY DEVICE
(FR) SUBSTRAT DE MATRICE, SON PROCÉDÉ DE FABRICATION ET DISPOSITIF D’AFFICHAGE
(ZH) 一种阵列基板、其制作方法及显示装置
Abstract:
(EN) A fabrication method for an array substrate, comprising: forming on a base substrate (4) a pattern comprising an active layer (1), a gate insulating layer (2), and a gate electrode (3); and employing a patterning process to form a pattern comprising an interlayer dielectric layer (8), a source electrode (9), a drain electrode (10), and a pixel electrode (11) on the base substrate (4) on which the pattern of the active layer (1), the gate insulating layer (2), and the gate electrode (3) is formed. Compared with a customary fabrication process in which an array substrate requires a passivation layer to be provided between a film layer where a source electrode and a drain electrode are located and a film layer where a pixel electrode is located and a total of four instances of masking for the formation of patterns of an interlayer dielectric layer, the source electrode, the drain electrode, the passivation layer, and the pixel electrode, this reduces the instances of masking and simplifies the fabrication process for the array substrate. Also provided are the array substrate and a display device.
(FR) L'invention concerne un procédé de fabrication, pour un substrat de matrice, qui consiste: à former, sur un substrat de base (4), un motif comportant une couche active (1), une couche d'isolation de grille (2) et une électrode de grille (3) ; à employer un processus de formation de motif pour former un motif comportant une couche diélectrique de couche intermédiaire (8), une électrode de source (9), une électrode déversoir (10) et une électrode de pixel (11) sur le substrat de base (4), sur lequel le motif de la couche active (1), de la couche d'isolation de grille (2) et de l'électrode de grille (3) est formé. Par comparaison avec un procédé de fabrication habituel dans lequel un substrat de matrice nécessite qu'une couche de passivation soit disposée entre une couche de film dans laquelle une électrode de source et une électrode déversoir sont situées et une couche de film dans laquelle une électrode de pixel est située, et un total de quatre instances de masquage pour la formation de motifs d'une couche diélectrique de couche intermédiaire, de l'électrode de source, de l'électrode déversoir, de la couche de passivation et de l'électrode de pixel, ceci permet de réduire les instances de masquage et simplifie le processus de fabrication pour le substrat de matrice. L'invention concerne en outre un substrat de matrice et un dispositif d'affichage.
(ZH) 一种阵列基板的制作方法,包括:在衬底基板(4)上形成包括有源层(1)、栅绝缘层(2)和栅极(3)的图形;在形成有有源层(1)、栅绝缘层(2)和栅极(3)的图形的衬底基板(4)上采用一次构图工艺形成包括层间介质层(8)、源极(9)、漏极(10)和像素电极(11)的图形。与惯常的阵列基板需要在源极和漏极所在膜层与像素电极所在膜层之间设置钝化层且层间介质层、源极、漏极、钝化层和像素电极的图形的形成总共需要经过四次掩模的制作过程相比,可以减少掩模的次数,简化阵列基板的制作工艺。还提供了一种阵列基板以及显示装置。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)