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1. (WO2017020362) TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/020362 International Application No.: PCT/CN2015/087912
Publication Date: 09.02.2017 International Filing Date: 24.08.2015
IPC:
H01L 21/77 (2017.01) ,H01L 27/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
Applicants: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.[CN/CN]; NO.9-2, Tangming Road, Guangming District of Shenzhen, Guangdong 518132, CN
Inventors: LU, Macai; CN
Agent: COMIPS INTELLECTUAL PROPERTY OFFICE; Room 15E, Shenkan Building, Shangbu Zhong Road, Futian District Shenzhen, Guangdong 518028, CN
Priority Data:
201510471923.X04.08.2015CN
Title (EN) TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF
(FR) SUBSTRAT DE TFT ET SON PROCÉDÉ DE FABRICATION
(ZH) TFT基板的制作方法及TFT基板
Abstract:
(EN) Disclosed are a TFT substrate and manufacturing method thereof. The manufacturing method performs etching on source and drain contact areas (311, 312) of polysilicon active layers (31, 32) until the heights thereof are less than the height of a middle trench area (313). The source and drain contact areas are designed as steps such that carriers are affected by an electric field (Vds electric field) in a direction deviated from an interface of polysilicon/gate insulating layers (4) in the proximity of the drain contact area, and thus migration paths are deviated from the interface of the polysilicon/gate insulating layers, reducing energetic carriers injected into the gate insulating layer. The existence of the step of the drain contact area reduces both the peak intensity of a transverse electric field (Vds electric field) in the proximity of the drain contact area and the intensity of a longitudinal electric field (Vgs electric field) of the drain contact area, such that a pinch-off point moves towards the drain contact area, reducing the threshold voltage drift and increasing the reliability of TFTs.
(FR) L’invention concerne un substrat de TFT et son procédé de fabrication. Le procédé de fabrication consiste à graver sur des zones de contact de source et de drain (311, 312) de couches actives de polysilicium (31, 32) jusqu’à de que leurs hauteurs soient inférieures à la hauteur d’une zone de tranchée centrale (313). Les zones de contact de source et de drain sont conçues en escalier de sorte que des porteurs de charge sont affectés par un champ électrique (champ électrique Vds) dans une direction déviée par rapport à une interface couche de polysilicium/couche isolante de grille (4) à proximité de la zone de contact de drain, et ainsi de chemins de migration sont déviés de l’interface couche de polysilicium/couche isolante de grille, réduisant les porteurs de charge énergétiques injectés dans la couche isolante de grille. L’existence de l’escalier de la zone de contact de drain réduit aussi bien l’intensité de crête d’un champ électrique transversal (champ électrique Vds) à proximité de la zone de contact de drain et l’intensité d’un champ électrique longitudinal (champ électrique Vgs) de la zone de contact de drain, de sorte qu’un point de pinçage se déplace vers la zone de contact de drain, réduisant la dérive de tension de seuil et accroissant la fiabilité de TFT.
(ZH) 一种TFT基板的制作方法及TFT基板,制作方法是通过对多晶硅有源层(31、32)的源、漏极接触区(311、312)进行蚀刻,使其高度低于中间沟道区(313)的高度,并且将所述源、漏极接触区设计为台阶状,使得载流子在漏极接触区附近受到偏离多晶硅/栅极绝缘层(4)界面方向电场的作用(Vds电场),迁移路径被拉离多晶硅/栅极绝缘层界面,减少高能载子注入栅极绝缘层内,并且由于漏极接触区的台阶的存在,使得漏极接触区附近横向电场(Vds电场)峰值强度以及漏极接触区纵向电场(Vgs电场)强度均下降,夹断点往漏极接触区边缘移动,减小阈值电压漂移,提高TFT可靠性。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)