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1. (WO2017020332) DRIVE CIRCUIT AND SHIFT REGISTER CIRCUIT
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/020332 International Application No.: PCT/CN2015/086737
Publication Date: 09.02.2017 International Filing Date: 12.08.2015
IPC:
G09G 3/36 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
Applicants: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.[CN/CN]; NO.9-2,Tangming Rd, Guangming New District Shenzhen City, Guangdong 518132, CN
WUHAN CHINA STAR OPTOELECTRONICE TECHNOLOGY CO., LTD[CN/CN]; Building C5 No.666 Gaoxin Avenue, East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors: HAO, Sikun; CN
Agent: CHINA WISPRO INTELLECTUAL PROPERTY LLP.; Room A806 Zhongdi Building, China University of Geosciences Base, No.8 Yuexing 3rd Road, High-Tech Industrial Estate, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201510475825.305.08.2015CN
Title (EN) DRIVE CIRCUIT AND SHIFT REGISTER CIRCUIT
(FR) CIRCUIT D'ATTAQUE ET CIRCUIT DE REGISTRE À DÉCALAGE
(ZH) 驱动电路以及移位寄存电路
Abstract:
(EN) A drive circuit (1) and a shift register circuit (10). The drive circuit (1) comprises multiple shift register circuits (10) that are disposed in a cascading mode. Each shift register circuit (10) comprises a transmission-gate lock circuit (11) and a signal transmission circuit (12). The transmission-gate lock circuit (11) comprises a transmission gate (112). A first clock signal (13) triggers the transmission gate (112), so that a previous second level transmission signal (Qn-2) is output to the signal transmission circuit (12) through the transmission gate (112) to form a current level transmission signal (Qn). A second clock signal (14) controls the current level transmission signal (Qn) to generate a current level gate driver signal (Gn) by using the signal transmission circuit (12). By means of the foregoing manner, the drive circuit (1) can be applicable to a CMOS process, and has low power consumption and a wide noise margin.
(FR) L'invention concerne un circuit d'attaque (1) et un circuit de registre à décalage (10). Le circuit d'attaque (1) comprend de multiples circuits de registre à décalage (10) qui sont disposés dans un mode en cascade. Chaque circuit de registre à décalage (10) comprend un circuit de verrouillage à grille de transmission (11) et un circuit de transmission de signal (12). Le circuit de verrouillage à grille de transmission (11) comprend une grille de transmission (112). Un premier signal d'horloge (13) déclenche la grille de transmission (112), de telle sorte qu'un signal précédent de transmission de second niveau (Qn-2) est délivré en sortie au circuit de transmission de signal (12) par la grille de transmission (112) pour former un signal de transmission de niveau actuel (Qn). Un second signal d'horloge (14) commande le signal de transmission de niveau actuel (Qn) pour générer un signal d'élément d'attaque de grille de niveau actuel (Gn) en utilisant le circuit de transmission de signal (12). Au moyen de la manière ci-dessus, le circuit d'attaque (1) peut être applicable à un processus CMOS, et a une faible consommation d'énergie et une large marge de bruit.
(ZH) 一种驱动电路(1)以及移位寄存电路(10)。该驱动电路(1)包括多个级联设置的移位寄存电路(10),每一移位寄存电路(10)包括传输门锁存电路(11)和信号传输电路(12),其中传输门锁存电路(11)包括一传输门(112),第一时钟信号(13)触发传输门(112),将前第二级传输信号(Qn-2)通过传输门(112)输出至信号传输电路(12),形成当前级传输信号(Qn);第二时钟信号(14)控制当前级传输信号(Qn)通过信号传输电路(12)产生当前级栅极驱动信号(Gn)。通过以上方式,所述驱动电路(1)能够适用于CMOS制程,功耗低、噪声容限宽。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)