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1. (WO2017019244) CONDUCTIVE SEAL RING FOR POWER DISTRIBUTION
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2017/019244 International Application No.: PCT/US2016/040160
Publication Date: 02.02.2017 International Filing Date: 29.06.2016
Chapter 2 Demand Filed: 07.06.2017
IPC:
H01L 23/58 (2006.01) ,H01L 23/522 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants: QUALCOMM INCORPORATED[US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors: BRINDLE, Christopher N.; US
ARRIAGADA, Anton; US
Agent: KELTON, Thomas W.; US
WEBB, Gregory P.; US
CHEN, Tom; US
MICHELSON, Gregory J.; US
HALLMAN, Jonathan; US
WELCH, Henry L.; US
FOWLES, Adam; US
NGUYEN, Thuc B.; US
EDWARDS, Gary J.; US
HOWISON, Will; US
LI, Eric; US
PATTANI, Pranay; US
HUH, Gregory; US
Priority Data:
14/809,14124.07.2015US
Title (EN) CONDUCTIVE SEAL RING FOR POWER DISTRIBUTION
(FR) BAGUE D'ÉTANCHÉITE CONDUCTRICE POUR DISTRIBUTION DE PUISSANCE
Abstract:
(EN) A multi-block semiconductor device includes a first block and a second block operating in different power regimes from each other. A seal ring is around a periphery of the die, hermetically sealing the first and second blocks. The die has a substrate and an insulating layer, the seal ring being on the insulating layer. The seal ring serves as a power bus for the first block but not the second block. The seal ring and first block are electrically coupled to a first ground node, the first ground node being electrically isolated at a die-level from other ground nodes in the multi-block semiconductor device. In some embodiments, the second block is located in a central area of the die, and a plurality of metal lines electrically connect the seal ring to the first block, the metal lines being evenly spaced around a majority of the periphery of the semiconductor die.
(FR) La présente invention concerne un dispositif à semi-conducteur multiblocs comprenant un premier bloc et un second bloc fonctionnant suivant des régimes de puissance différents l'un de l'autre. Une bague d'étanchéité est située autour de la périphérie de la puce, scellant hermétiquement les premier et second blocs. La puce comporte un substrat et une couche isolante, la bague d'étanchéité étant sur la couche isolante. La bague d'étanchéité sert de bus de puissance pour le premier bloc mais pas pour le second bloc. La bague d'étanchéité et le premier bloc sont électriquement couplés à un premier nœud de mise à la terre, le premier nœud de mise à la terre étant électriquement isolé, au niveau de la pice, d'autres nœuds de mise à la terre dans le dispositif à semi-conducteur multiblocs. Dans certains modes de réalisation, le second bloc est situé dans une zone centrale de la puce et une pluralité de lignes métalliques connectent électriquement la bague d'étanchéité au premier bloc, les lignes métalliques étant régulièrement espacées autour de la majeure partie de la périphérie de la puce à semi-conducteur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)