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1. (WO2017019219) CLOCK GATING USING A DELAY CIRCUIT

Pub. No.:    WO/2017/019219    International Application No.:    PCT/US2016/039568
Publication Date: Fri Feb 03 00:59:59 CET 2017 International Filing Date: Tue Jun 28 01:59:59 CEST 2016
IPC: G06F 1/10
G06F 1/32
H03K 5/00
Applicants: QUALCOMM INCORPORATED
Inventors: HAMDAN, Fadi Adel
Title: CLOCK GATING USING A DELAY CIRCUIT
Abstract:
An apparatus includes a latch of a clock gating circuit (CGC). The latch is configured to generate a first signal in response to a clock signal. The apparatus further includes a delay circuit of the CGC. The delay circuit is configured to receive the clock signal and to generate a second signal based on the clock signal and the first signal. The apparatus further includes an output circuit of the CGC. The output circuit is coupled to the delay circuit and to the latch. The output circuit is configured to generate a master clock signal based on the clock signal and the second signal. An edge of the master clock signal is delayed with respect to an edge of the clock signal based on a delay characteristic associated with a slave clock signal.