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1. (WO2017018600) FLEXIBLE SUBSTRATE HAVING THROUGH-HOLES FILLED WITH CONDUCTIVE MATERIAL AND MANUFACTURING METHOD OF SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/018600 International Application No.: PCT/KR2015/011003
Publication Date: 02.02.2017 International Filing Date: 19.10.2015
IPC:
H01L 21/768 (2006.01) ,H01L 21/027 (2006.01) ,H01L 21/304 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
Applicants:
한국기계연구원 KOREA INSTITUTE OF MACHINERY & MATERIALS [KR/KR]; 대전시 유성구 가정북로 156 156, Gajeongbuk-ro Yuseong-gu Daejeon 305-343, KR
Inventors:
김용진 KIM, Yong-jin; KR
이재학 LEE, Jae-hak; KR
이주용 LEE, Ju-yong; KR
송준엽 SONG, Joon-yub; KR
김승만 KIM, Seung-man; KR
이창우 LEE, Chang-woo; KR
하태호 HA, Tae-ho; KR
Agent:
김민태 KIM, Min-tae; KR
Priority Data:
10-2015-010483524.07.2015KR
Title (EN) FLEXIBLE SUBSTRATE HAVING THROUGH-HOLES FILLED WITH CONDUCTIVE MATERIAL AND MANUFACTURING METHOD OF SAME
(FR) SUBSTRAT FLEXIBLE AYANT DES TROUS TRAVERSANTS REMPLIS DE MATÉRIAU CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(KO) 도전물이 매립된 관통홀을 갖는 유연 기판 및 이의 제조방법
Abstract:
(EN) Disclosed are a flexible substrate and a manufacturing method of same, the flexible substrate comprising a polymer substrate, a penetrating conductive material, an upper conductive material and a lower conductive material. The polymer substrate has through-holes penetrating according to a predetermined pattern formed via photolithography. The penetrating conductive material is formed by filling the through-holes in the polymer substrate. The upper conductive material is planarized, so as to level the upper surface of the polymer substrate and the upper surface of the penetrating conductive material, and patterned. The lower conductive material is planarized, so as to level the lower surface of the polymer substrate and the lower surface of the penetrating conductive material, and patterned.
(FR) L'invention concerne un substrat flexible et son procédé de fabrication, le substrat flexible comprenant un substrat polymère, un matériau conducteur pénétrant, un matériau conducteur supérieur et un matériau conducteur inférieur. Le substrat polymère est doté de trous traversants pénétrant selon un motif prédéterminé formé par photolithographie. Le matériau conducteur pénétrant est formé en remplissant les trous traversants dans le substrat polymère. Le matériau conducteur supérieur est aplani, de manière à niveler la surface supérieure du substrat polymère et la surface supérieure du matériau conducteur pénétrant, et muni d'un motif. Le matériau conducteur inférieur est aplani, de manière à niveler la surface inférieure du substrat polymère et la surface inférieure du matériau conducteur pénétrant, et muni d'un motif.
(KO) 유연기판 및 이의 제조방법에서, 상기 유연기판은 폴리머 기판, 관통 도전물, 상부 도전물 및 하부 도전물을 포함한다. 상기 폴리머 기판은 노광공정(photolithography)을 통해 형성된 일정 패턴에 따라 관통하는 관통홀을 가진다. 상기 관통 도전물을 상기 폴리머 기판의 관통홀을 매립하며 형성된다. 상기 상부 도전물은 상기 폴리머 기판의 상부 표면과 상기 관통 도전물의 상부 표면이 평면을 이루도록 평탄화 및 패터닝된다. 상기 하부 도전물은 상기 폴리머 기판의 하부 표면과 상기 관통 도전물의 하부 표면이 평면을 이루도록 평탄화 및 패터닝된다.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)