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1. (WO2017015970) LTPS ARRAY PANEL AND MANUFACTURING METHOD THEREOF
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2017/015970 International Application No.: PCT/CN2015/085660
Publication Date: 02.02.2017 International Filing Date: 31.07.2015
IPC:
H01L 27/12 (2006.01) ,H01L 21/336 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.[CN/CN]; No. 9-2,Tangming Rd, Guangming New District Shenzhen, Guangdong 518132, CN
WUHAN CHINA STAR OPTOELECTRONICE TECHNOLOGY CO., LTD[CN/CN]; Building C5 No.666 Gaoxin Avenue East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors: WANG, Cong; CN
DU, Peng; CN
WANG, Xiaoxiao; CN
Agent: CHINA WISPRO INTELLECTUAL PROPERTY LLP.; Room A806 Zhongdi Building, China University of Geosciences Base No.8 Yuexing 3rd Road, High-Tech Industrial Estate, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201510443670.524.07.2015CN
Title (EN) LTPS ARRAY PANEL AND MANUFACTURING METHOD THEREOF
(FR) PANNEAU DE RÉSEAU LTPS ET SON PROCÉDÉ DE FABRICATION
(ZH) LTPS阵列基板及其制造方法
Abstract:
(EN) A low temperature polysilicon (LTPS) array panel and a manufacturing method thereof. The method comprises: forming a source and a drain on a substrate (21); forming a polysilicon layer having a first area and a second area on the substrate (21) comprising the source and drain, wherein the first area of the polysilicon layer has a thickness exceeding that of the second area, and a polysilicon layer portion in the first area covers the source and drain; performing a passivation process on a surface of the polysilicon layer to convert portions close to surfaces of the first area and the second area of the polysilicon layer into an insulation layer (24); and forming a gate on the insulation layer (24) between the source and drain. The method can simplify LTPS process and reduce manufacturing costs.
(FR) L'invention concerne un panneau de réseau de polysilicium à basse température (LTPS) et son procédé de fabrication. Le procédé consiste à : former une source et un drain sur un substrat (21) ; former une couche de polysilicium ayant une première zone et une seconde zone sur le substrat (21) comprenant la source et un drain, laquelle première zone de la couche de polysilicium a une épaisseur supérieure à celle de la seconde zone, et une partie de couche de polysilicium dans la première zone recouvrant la source et de drain ; effectuer un procédé de passivation sur une surface de la couche de polysilicium pour convertir des parties proches des surfaces de la première zone et de la seconde zone de la couche de polysilicium en couche isolante (24) ; et former une grille sur la couche isolante (24) entre la source et le drain. Le procédé peut simplifier le procédé LTPS et réduire les coûts de fabrication.
(ZH) 一种LTPS阵列基板及其制造方法。该方法包括:在基体(21)上形成源极和漏极;在包括源极和漏极的基体(21)上形成第一区域和第二区域的多晶硅层(22),且第一区域的多晶硅层的厚度大于第二区域的,第一区域的多晶硅层部分覆盖源极和漏极;对多晶硅层的表面进行钝化处理,以将第二区域的多晶硅层以及第一区域的多晶硅层临近表面的部分变成绝缘层(24);在源极和漏极之间的绝缘层(24)上形成栅极。能够简化LTPS工艺制程并降低生产成本。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)