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1. WO2017005761 - METHOD FOR MANAGING A DISTRIBUTED CACHE

Publication Number WO/2017/005761
Publication Date 12.01.2017
International Application No. PCT/EP2016/065897
International Filing Date 06.07.2016
IPC
G06F 12/08 2016.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G06F 12/12 2016.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
12Replacement control
CPC
G06F 12/0868
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0866for peripheral storage systems, e.g. disk cache
0868Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F 12/0897
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0893Caches characterised by their organisation or structure
0897with two or more cache hierarchy levels
G06F 12/12
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
12Replacement control
G06F 12/123
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
12Replacement control
121using replacement algorithms
123with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
G06F 2212/214
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
21Employing a record carrier using a specific recording technology
214Solid state disk
Applicants
  • ALCATEL LUCENT [FR]/[FR]
Inventors
  • GALLO, Massimo
  • PERINO, Diego
  • SAINO, Lorenzo
Agents
  • BERTHIER, Karine
Priority Data
15002008.906.07.2015EP
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METHOD FOR MANAGING A DISTRIBUTED CACHE
(FR) PROCÉDÉ DE GESTION D'ANTÉMÉMOIRE RÉPARTIE
Abstract
(EN) A method for managing a multiple level cache of a host comprising a primary cache which is a volatile memory such as a DRAM memory and a secondary cache which is a non-volatile memory such as a SSD memory. The method comprises, if a segment identification data has been computed in said segment hash table, a corresponding processing core checks whether a corresponding packet is stored in a first portion of a primary cache or in a second portion of a secondary cache, - if the packet is stored in said first portion, said corresponding packet is sent back to a requester and a request counter is incremented, a DRAM segment map pointer entering in a DRAM-LRU linked list, the DRAM segment map pointer being prioritized by being moved on top of said DRAM-LRU linked list, - if the packet is stored in said second portion, said corresponding packet is passed to an SSD core so as to copy the entire given segment from the secondary cache to the primary cache; then said request is passed back to said corresponding processing core in order to create the DRAM segment map pointer for pointing to the first portion storing said corresponding packet so as to be entered in said DRAM-LRU linked list, the SSD segment map pointer being also entered in said SSD-LRU linked list, the DRAM segment map pointer and the SSD segment map pointer being respectively prioritized by being respectively moved on top of said DRAM-LRU linked list and said SSD-LRU linked list; then said corresponding packet is sent back to said requester.
(FR) L'invention concerne un procédé de gestion d'une antémémoire multiniveau d'un hôte comprenant une antémémoire primaire qui est une mémoire volatile telle qu'une mémoire DRAM et une antémémoire secondaire qui est une mémoire non volatile telle qu'une mémoire SSD. Le procédé consiste, si des données d'identification de segment ont été calculées dans ladite table de hachage de segment, à vérifier, par un noyau de traitement correspondant, si un paquet correspondant est mémorisé dans une première partie d'une antémémoire primaire ou dans une seconde partie d'une antémémoire secondaire, - si le paquet est mémorisé dans ladite première partie, à renvoyer ledit paquet correspondant à un demandeur et à incrémenter un compteur de demandes, un pointeur de correspondance de segment de DRAM entrant dans une liste de liaison DRAM-LRU, le pointeur de correspondance de segment de DRAM faisant l'objet d'une attribution de priorité en étant amené en haut de ladite liste de liaison DRAM-LRU, - si le paquet est mémorisé dans ladite seconde partie, à transmettre ledit paquet correspondant à un noyau SSD de façon à copier la totalité du segment donné de l'antémémoire secondaire vers l'antémémoire primaire; puis, à retransmettre ladite demande audit noyau de traitement correspondant afin de créer le pointeur de correspondance de segment de DRAM pour pointer la première partie mémorisée dans ledit paquet correspondant de façon à l'entrer dans ladite liste de liaison DRAM-LRU, le pointeur de correspondance de segment de SSD étant également entré dans ladite liste de liaison SSD-LRU, le pointeur de correspondance de segment de DRAM et le pointeur de correspondance de segment de SSD étant respectivement classés par ordre de priorité par déplacement respectif en haut de ladite liste de liaison DRAM-LRU et de ladite liste de liaison SSD-LRU; à renvoyer ensuite ledit paquet correspondant audit demandeur.
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