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1. (WO2017003959) TECHNIQUES FOR FILAMENT LOCALIZATION, EDGE EFFECT REDUCTION, AND FORMING/SWITCHING VOLTAGE REDUCTION IN RRAM DEVICES
Available information on National Phase entries(more information)
OfficeEntry DateNational NumberNational Status
Republic of Korea 23.01.20181020187002084Published: 06.03.2018
European Patent Office2016818561Published: 16.05.2018
Withdrawn: 19.03.2019