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1. (WO2017003959) TECHNIQUES FOR FILAMENT LOCALIZATION, EDGE EFFECT REDUCTION, AND FORMING/SWITCHING VOLTAGE REDUCTION IN RRAM DEVICES
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/003959 International Application No.: PCT/US2016/039681
Publication Date: 05.01.2017 International Filing Date: 27.06.2016
IPC:
H01L 21/76 (2006.01) ,H01L 23/48 (2006.01) ,H01L 23/52 (2006.01) ,H01L 29/40 (2006.01) ,H01L 45/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, California 95054, US
Inventors:
PILLARISETTY, Ravi; US
MAJHI, Prashant; US
SHAH, Uday; US
MUKHERJEE, Niloy; US
KARPOV, Elijah; US
DOYLE, Brian; US
CHAU, Robert; US
Agent:
PARKER, Wesley E.; US
Priority Data:
14/752,93427.06.2015US
Title (EN) TECHNIQUES FOR FILAMENT LOCALIZATION, EDGE EFFECT REDUCTION, AND FORMING/SWITCHING VOLTAGE REDUCTION IN RRAM DEVICES
(FR) TECHNIQUES DE LOCALISATION DE FILAMENTS, RÉDUCTION DE L'EFFET DE BORD, ET RÉDUCTION DE LA TENSION D'ÉCRITURE/COMMUTATION DANS LES DISPOSITIFS RRAM
Abstract:
(EN) The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer.
(FR) La présente invention concerne un système et un procédé pour former un dispositif de mémoire vive résistive (RRAM). Un dispositif RRAM conforme à la présente invention comprend un substrat et une première électrode disposée sur celui-ci. Le dispositif RRAM comprend une seconde électrode disposée sur la première électrode et une couche diélectrique RRAM disposée entre la première électrode et la seconde électrode. La couche diélectrique RRAM présente un évidement au niveau d'une partie centrale supérieure à l'interface entre la seconde électrode et la couche diélectrique RRAM.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN107636822KR1020180022835EP3320556