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1. (WO2017001650) EMBEDDED TEST CIRCUIT FOR PHYSICALLY UNCLONABLE FUNCTION
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2017/001650 International Application No.: PCT/EP2016/065479
Publication Date: 05.01.2017 International Filing Date: 01.07.2016
IPC:
H04L 9/32 (2006.01) ,H04L 9/08 (2006.01) ,G09C 1/00 (2006.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9
Arrangements for secret or secure communication
32
including means for verifying the identity or authority of a user of the system
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9
Arrangements for secret or secure communication
06
the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
08
Key distribution
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
C
CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
1
Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
Applicants:
SECURE-IC SAS [FR/FR]; 15, rue Claude Chappe ZAC des Champs Blancs 35510 Cesson-Sévigné, FR
Inventors:
DAFALI, Rachid; FR
DANGER, Jean-Luc; FR
GUILLEY, Sylvain; FR
LOZAC'H, Florent; FR
Agent:
HNICH-GASRI, Naïma; FR
Priority Data:
15306063.701.07.2015EP
Title (EN) EMBEDDED TEST CIRCUIT FOR PHYSICALLY UNCLONABLE FUNCTION
(FR) CIRCUIT D'ESSAI INCORPORÉ POUR UNE FONCTION PHYSIQUEMENT NON CLONABLE
Abstract:
(EN) There is disclosed a silicon integrated circuit comprising a Physically Unclonable Function and an online or embedded test circuit, said online test circuit comprising one or more circuit parts being physically adjacent to said PUF and said one or more circuits embodying one or more tests which can be performed to determine one or more quality properties of said PUF or otherwise characterize it. Different tests with specific associated method steps are described.
(FR) L’invention concerne un circuit intégré au silicium comprenant une fonction physiquement non clonable (PUF) et un circuit d'essai en ligne ou incorporé, ledit circuit d'essai en ligne comprenant une ou plusieurs partie(s) de circuit qui est/sont physiquement adjacente(s) à ladite PUF et ledit ou lesdits circuit(s) incorporant un ou plusieurs essai(s) qui peut/peuvent être réalisé(s) pour déterminer une ou plusieurs propriété(s) de qualité de ladite PUF ou autrement la caractériser. Différents essais ayant des étapes de procédé associé spécifiques sont décrits.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
KR1020180050276US20180183613CN108028757