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1. (WO2016209263) GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE
Latest bibliographic data on file with the International Bureau

Pub. No.: WO/2016/209263 International Application No.: PCT/US2015/037987
Publication Date: 29.12.2016 International Filing Date: 26.06.2015
IPC:
H01L 29/778 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
THEN, Han Wui; US
DASGUPTA, Sansaptak; US
GARDNER, Sanaz K.; US
RADOSAVLJEVIC, Marko; US
SUNG, Seung Hoon; US
CHAU, Robert S.; US
Agent:
BRODSKY, Stephen I.; US
Priority Data:
Title (EN) GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE
(FR) STRUCTURES DE TRANSISTOR AU NITRURE DE GALLIUM (GAN) SUR UN SUBSTRAT
Abstract:
(EN) Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.
(FR) L'invention concerne des techniques d'isolation d'oxyde de nitrure de gallium (GaN) et de formation de structures de transistors GaN sur un substrat. Dans certains cas, les structures de transistors GaN peuvent être utilisées pour une intégration de système sur puce de commutateurs radiofréquence (RF) d'extrémité avant GaN haute tension sur un substrat en silicium massif. Les techniques peuvent comprendre, par exemple, la formation de multiples ailettes dans un substrat, le dépôt de la couche de GaN sur les ailettes, l'oxydation d'au moins une partie de chaque ailette dans un espace au-dessous de la couche de GaN, et la formation d'un ou de plusieurs transistors sur et/ou à partir de la couche de GaN. Dans certains cas, la couche de GaN est une pluralité d'îlots de GaN, chaque îlot correspondant à une ailette donnée. Les techniques peuvent être utilisées pour former diverses architectures de transistors GaN isolées non planes ayant un facteur de forme relativement petit, une faible résistance à l'état passant, et une faible fuite à l'état bloqué, dans certains cas.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)
Also published as:
CN107660313KR1020180021123EP3314657US20180175184