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1. (WO2016164319) MULTIPLE BIT LINE VOLTAGE SENSING FOR NON-VOLATILE MEMORY
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2016/164319 International Application No.: PCT/US2016/025918
Publication Date: 13.10.2016 International Filing Date: 04.04.2016
IPC:
G11C 16/34 (2006.01) ,G11C 11/56 (2006.01) ,G11C 16/24 (2006.01) ,G11C 16/26 (2006.01) ,G11C 16/04 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
34
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56
using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
24
Bit-line control circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
26
Sensing or reading circuits; Data output circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
04
using variable threshold transistors, e.g. FAMOS
Applicants:
SanDisk Technologies LLC [US/US]; 6900 Dallas Parkway Suite 325 Plano, Texas 75024, US
Inventors:
DUTTA, Deepanshu; US
TSENG, Huai-Yuan; US
LEE, Dana; US
OOWADA, Ken; US
LEE, Shih-Chung; US
Agent:
MAGEN, BURT; Vierra Magen Marcus LLP 575 Market Street, Suite 3750 San Francisco, California 94105, US
Priority Data:
14/817,76704.08.2015US
62/144,83108.04.2015US
Title (EN) MULTIPLE BIT LINE VOLTAGE SENSING FOR NON-VOLATILE MEMORY
(FR) DÉTECTION DE TENSION DE LIGNE DE BITS MULTIPLES POUR MÉMOIRE NON VOLATILE
Abstract:
(EN) A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The one or more control circuits are configured to apply a reference voltage to the word lines of the memory cells. While applying the reference voltage to the wordlines of the plurality of memory cells, the one or more control circuits are configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to different bit lines connected to the different memory cells.
(FR) L'invention concerne un système de mémoire non volatile qui comprend une pluralité de cellules mémoire agencées en une structure tridimensionnelle et un ou plusieurs circuits de commande en communication avec les cellules mémoire. Lesdits circuits de commande sont configurés pour programmer et vérifier la programmation des cellules mémoire. Lesdits circuits de commande sont configurés pour appliquer une tension de référence sur les lignes de mots des cellules mémoire. Lors de l'application de la tension de référence sur les lignes de mots de la pluralité de cellules mémoire, lesdits circuits de commande sont configurés pour détecter si des cellules mémoire différentes de la pluralité de cellules mémoire sont dans différents états de données en appliquant différentes tensions de lignes de bits sur différentes lignes de bits connectées aux différentes cellules mémoire.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)