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1. WO2016151874 - NONVOLATILE SEMICONDUCTOR MEMORY

Publication Number WO/2016/151874
Publication Date 29.09.2016
International Application No. PCT/JP2015/068825
International Filing Date 30.06.2015
IPC
G11C 11/15 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
14using thin-film elements
15using multiple magnetic layers
G11C 13/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
CPC
G11C 11/1659
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
165Auxiliary circuits
1659Cell access
G11C 11/1675
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
165Auxiliary circuits
1675Writing or programming circuits or methods
G11C 11/1693
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
165Auxiliary circuits
1693Timing circuits or methods
G11C 11/1697
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
02using magnetic elements
16using elements in which the storage effect is based on magnetic spin effect
165Auxiliary circuits
1697Power supply circuits
G11C 13/00
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
Applicants
  • 株式会社 東芝 KABUSHIKI KAISHA TOSHIBA [JP]/[JP]
Inventors
  • 高谷 聡 TAKAYA, Satoshi
  • 野口 紘希 NOGUCHI, Hiroki
  • 藤田 忍 FUJITA, Shinobu
Agents
  • 特許業務法人スズエ国際特許事務所 S & S INTERNATIONAL PPC
Priority Data
2015-05804720.03.2015JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) NONVOLATILE SEMICONDUCTOR MEMORY
(FR) MÉMOIRE NON VOLATILE À SEMI-CONDUCTEURS
(JA) 不揮発性半導体メモリ
Abstract
(EN)
According to an embodiment of the present invention, nonvolatile semiconductor memory is provided with: a write circuit (13a-0) that generates a write current (Iw(t)) that changes the resistance value of a memory cell (MC) from a first resistance value to a second resistance value; a first current generating circuit (T11(y1)) that generates a first current (Iw'(t)) on the basis of the write current (Iw(t)) flowing to the memory cell (MC); a second current generating circuit (T13(y3)) that generates a second current (Iw'(t)×α) on the basis of the write current (Iw(t)) flowing to the memory cell (MC); a hold circuit (22) that holds a first value generated on the basis of the second current (Iw'(t)×α) at a time when the resistance value of the memory cell (MC) is the first resistance value; and a comparator (23) that compares a second value and the first value with each other, said second value having been generated on the basis of the first current (Iw'(t)) in a process where the resistance value of the memory cell (MC) changes from the first resistance value to the second resistance value.
(FR)
Selon un mode de réalisation de la présente invention, une mémoire non volatile à semi-conducteurs comprend : un circuit d'écriture (13a-0) qui génère un courant d'écriture (Iw(t)) qui change la valeur de résistance d'une cellule de mémoire (MC) d'une première valeur de résistance à une seconde valeur de résistance ; un premier circuit de génération de courant (T11(y1)) qui génère un premier courant (Iw'(t)) sur la base du courant d'écriture (Iw(t)) circulant vers la cellule de mémoire (MC) ; un second circuit de génération de courant (T13(y3)) qui génère un second courant (Iw'(t)×α) sur la base du courant d'écriture (Iw(t)) circulant vers la cellule de mémoire (MC) ; un circuit de maintien (22) qui maintient une première valeur générée sur la base du second courant (Iw'(t)×α) à un instant auquel la valeur de résistance de la cellule de mémoire (MC) est la première valeur de résistance ; et un comparateur (23) qui compare une seconde valeur et la première valeur l'une avec l'autre, ladite seconde valeur ayant été générée sur la base du premier courant (Iw'(t)) dans un processus dans lequel la valeur de résistance de la cellule de mémoire (MC) change de la première valeur de résistance à la seconde valeur de résistance.
(JA)
 実施形態に係わる不揮発性半導体メモリは、メモリセル(MC)を第1の抵抗値から第2の抵抗値に変化させる書き込み電流(Iw(t))を生成する書き込み回路(13a-0)と、メモリセル(MC)に流れる書き込み電流(Iw(t))に基づいて第1の電流(Iw'(t))を生成する第1の電流生成回路(T11(y1))と、メモリセル(MC)に流れる書き込み電流(Iw(t))に基づいて第2の電流(Iw'(t)×α)を生成する第2の電流生成回路(T13(y3))と、メモリセル(MC)が第1の抵抗値のときの第2の電流(Iw'(t)×α)に基づいて生成される第1の値を保持するホールド回路(22)と、メモリセル(MC)が第1の抵抗値から第2の抵抗値に変化する過程での第1の電流(Iw'(t))に基づいて生成される第2の値と第1の値とを比較する比較器(23)と、を備える。
Also published as
CN201580046348.7
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