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1. WO2016144724 - APPARATUSES AND METHODS FOR SHIFT DECISIONS

Publication Number WO/2016/144724
Publication Date 15.09.2016
International Application No. PCT/US2016/020828
International Filing Date 04.03.2016
IPC
G11C 7/06 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
06Sense amplifiers; Associated circuits
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G11C 11/4076
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4076Timing circuits
G11C 11/4087
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
4087Address decoders, e.g. bit - or word line decoders; Multiple line decoders
G11C 11/4091
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/4093
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4093Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 7/1006
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • HUSH, Glen E.
Agents
  • WADDICK, Kevin G.
Priority Data
62/130,71310.03.2015US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) APPARATUSES AND METHODS FOR SHIFT DECISIONS
(FR) APPAREILS ET PROCÉDÉS POUR DÉCISIONS DE DÉCALAGE
Abstract
(EN)
The present disclosure includes apparatuses and methods for shift decisions. An example apparatus includes a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement logical operations and a decision component configured to implement a shift of data based on a determined functionality of a memory cell in the array.
(FR)
La présente invention concerne des appareils et des procédés pour des décisions de décalage. Un appareil donné à titre d'exemple comprend un dispositif mémoire. Le dispositif mémoire comprend un réseau de cellules mémoire et un circuit de détection couplé au réseau par l'intermédiaire d'une pluralité de lignes de détection. Le circuit de détection comprend un amplificateur de détection et un élément de calcul couplé à une ligne de détection et configuré pour mettre en œuvre des opérations logiques et un élément de décision configuré pour mettre en œuvre un décalage de données sur la base d'une fonctionnalité déterminée d'une cellule mémoire dans le réseau.
Also published as
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