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1. WO2016140516 - TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF

Publication Number WO/2016/140516
Publication Date 09.09.2016
International Application No. PCT/KR2016/002094
International Filing Date 02.03.2016
IPC
H03M 13/11 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
H03M 13/27 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
27using interleaving techniques
CPC
H03M 13/1148
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
H03M 13/1165
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
116Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
1165QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
H03M 13/152
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13Linear codes
15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
151using error location or error correction polynomials
152Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/255
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
25Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
255with Low Density Parity Check [LDPC] codes
H03M 13/2707
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
27using interleaving techniques
2703the interleaver involving at least two directions
2707Simple row-column interleaver, i.e. pure block interleaving
H03M 13/2778
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
27using interleaving techniques
2778Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
Applicants
  • SAMSUNG ELECTRONICS CO., LTD. [KR]/[KR]
Inventors
  • JEONG, Hong-sil
  • KIM, Kyung-joong
  • MYUNG, Se-ho
Agents
  • JEONG, Hong-sik
Priority Data
10-2015-013718227.09.2015KR
62/127,02202.03.2015US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF
(FR) ÉMETTEUR ET PROCÉDÉ DE PERMUTATION DE PARITÉ DE CELUI-CI
Abstract
(EN)
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to puncture some of the parity bits in the group-wise interleaved bit groups, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups.
(FR)
La présente invention se rapporte à un émetteur. L'émetteur comprend : un codeur de contrôle de parité à faible densité (LDPC) configuré pour coder des bits d'entrée pour générer des bits de parité ; un permutateur de parité configuré pour assurer la permutation de parité par entrelacement des bits de parité et entrelacement par groupes d'une pluralité de groupes de bits comprenant les bits de parité entrelacés ; et un poinçonneur configuré pour poinçonner certain des bits de parité des groupes de bits entrelacés par groupes, le permutateur de parité entrelaçant par groupes les groupes de bits de sorte que certains des groupes de bits soient respectivement positionnés à des endroits prédéterminés, et que le reste des groupes de bits soit positionné sans ordre dans le groupe de bits entrelacés par groupes.
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