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1. WO2016140515 - TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF

Publication Number WO/2016/140515
Publication Date 09.09.2016
International Application No. PCT/KR2016/002093
International Filing Date 02.03.2016
IPC
H03M 13/27 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
27using interleaving techniques
H03M 13/11 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
CPC
H03M 13/1148
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
H03M 13/1165
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
116Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
1165QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
H03M 13/1177
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
1177Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
H03M 13/152
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13Linear codes
15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
151using error location or error correction polynomials
152Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/255
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
25Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
255with Low Density Parity Check [LDPC] codes
H03M 13/2707
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
27using interleaving techniques
2703the interleaver involving at least two directions
2707Simple row-column interleaver, i.e. pure block interleaving
Applicants
  • SAMSUNG ELECTRONICS CO., LTD. [KR]/[KR]
Inventors
  • KIM, Kyung-joong
  • MYUNG, Se-ho
  • JEONG, Hong-sil
Agents
  • JEONG, Hong-sik
Priority Data
10-2015-013718527.09.2015KR
62/127,05602.03.2015US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF
(FR) ÉMETTEUR ET PROCÉDÉ DE PERMUTATION DE PARITÉ ASSOCIÉ
Abstract
(EN)
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.
(FR)
La présente invention se rapporte à un émetteur. L'émetteur comprend : un codeur à contrôle de parité de faible densité (LDPC) configuré pour coder des bits d'entrée afin de générer des bits de parité; un permutateur de parité configuré pour réaliser une permutation de parité par entrelacement des bits de partié et entrelacement groupe par groupe d'une pluralité de groupes de bits comprenant les bits de parité entrelacés; et un dispositif de poinçonnage configuré pour sélectionner certains des bits de parité dans les groupes de bits entrelacés groupe par groupe et poinçonner les bits de parité sélectionnés, le permutateur de parité entrelaçant groupe par groupe les groupes de bits de telle sorte que certains des groupes de bits sont respectivement positionnés en des emplacements prédéterminés, et un reste de groupes de bits est positionné sans ordre dans les groupes de bits entrelacés groupe par groupe de sorte que le dispositif de poinçonnage sélectionne des bits de parité compris dans certains des groupes de bits positionnés en des emplacements prédéterminés, séquentiellement, et sélectionne des bits de parité compris dans le reste des groupes de bits sans ordre.
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