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1. WO2016140509 - TRANSMITTER AND SHORTENING METHOD THEREOF

Publication Number WO/2016/140509
Publication Date 09.09.2016
International Application No. PCT/KR2016/002086
International Filing Date 02.03.2016
IPC
H03M 13/15 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13Linear codes
15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem codes
H03M 13/11 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
CPC
H03M 13/1102
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
H03M 13/1165
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
116Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
1165QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
H03M 13/152
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13Linear codes
15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
151using error location or error correction polynomials
152Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/253
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
25Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
253with concatenated codes
H03M 13/255
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
25Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
255with Low Density Parity Check [LDPC] codes
H03M 13/2906
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
29combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
2906using block codes
Applicants
  • SAMSUNG ELECTRONICS CO., LTD. [KR]/[KR]
Inventors
  • JEONG, Hong-sil
  • KIM, Kyung-joong
  • MYUNG, Se-ho
Agents
  • JEONG, Hong-sik
Priority Data
10-2015-013718327.09.2015KR
62/127,02302.03.2015US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TRANSMITTER AND SHORTENING METHOD THEREOF
(FR) ÉMETTEUR ET SON PROCÉDÉ DE RACCOURCISSEMENT
Abstract
(EN)
A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, determine whether a number of the outer-encoded bits satisfies a predetermined number of bits required according to at least one of a code rate and a code length for Low Density Parity Check (LDPC) encoding, pads zero bits to some of the bits in the bit groups if the number of the outer-encoded bits is less than the predetermined number of bits, and maps the outer-encoded bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute LDPC information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the some of the bits, in which zero bits are padded, are included in some of the bit groups which are not sequentially disposed in the LDPC information bits.
(FR)
La présente invention se rapporte à un émetteur. L'émetteur comprend : un codeur externe configuré pour coder des bits d'entrée pour générer des bits à codage externe comprenant les bits d'entrée et des bits de parité ; un dispositif de remplissage de zéro configuré pour générer une pluralité de groupes de bits, chacun d'entre eux étant constitué d'un même nombre de bits, pour déterminer si un certain nombre de bits à codage externe satisfait à un nombre prédéterminé de bits requis selon un débit de code et/ou une longueur de code pour un codage à contrôle de parité et faible densité (LDPC), pour remplir des bits de zéro sur certains des bits dans les groupes de bits si le nombre de bits à codage externe est inférieur au nombre prédéterminé de bits, et pour mapper les bits à codage externe avec les bits restants dans les groupes de bits, en se basant sur un schéma de raccourcissement prédéterminé, pour ainsi constituer des bits d'information LDPC ; et un codeur LDPC configuré pour coder les bits d'information LDPC, lesdits certains bits, dans lesquels des bits de zéro sont remplis, étant inclus dans certains des groupes de bits qui ne sont pas disposés de manière séquentielle dans les bits d'information LDPC.
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