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1. WO2016140504 - TRANSMITTER AND SHORTENING METHOD THEREOF

Publication Number WO/2016/140504
Publication Date 09.09.2016
International Application No. PCT/KR2016/002074
International Filing Date 02.03.2016
IPC
H03M 13/15 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13Linear codes
15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem codes
H03M 13/11 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
CPC
G06F 11/1004
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1004to protect a block of data words, e.g. CRC or checksum
H03M 13/1148
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
H03M 13/1157
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
1157Low-density generator matrices [LDGM]
H03M 13/1165
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1148Structural properties of the code parity-check or generator matrix
116Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
1165QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
H03M 13/1191
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
1191Codes on graphs other than LDPC codes
H03M 13/152
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
13Linear codes
15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
151using error location or error correction polynomials
152Bose-Chaudhuri-Hocquenghem [BCH] codes
Applicants
  • SAMSUNG ELECTRONICS CO., LTD. [KR]/[KR]
Inventors
  • KIM, Kyung-joong
  • MYUNG, Se-ho
  • JEONG, Hong-sil
Agents
  • JEONG, Hong-sik
Priority Data
10-2015-013718127.09.2015KR
62/126,99902.03.2015US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TRANSMITTER AND SHORTENING METHOD THEREOF
(FR) ÉMETTEUR ET SON PROCÉDÉ DE RACCOURCISSEMENT
Abstract
(EN)
A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.
(FR)
La présente invention se rapporte à un émetteur. L'émetteur comprend : un codeur externe configuré pour coder des bits d'entrée pour générer des bits à codage externe comprenant les bits d'entrée et des bits de parité ; un dispositif de remplissage de zéro configuré de manière à constituer des bits d'information à contrôle de parité et faible densité (LDPC) comprenant les bits à codage externe et des bits de zéro ; et un codeur LDPC configuré pour coder les bits d'information LDPC, lesquels bits d'information LDPC sont divisés en une pluralité de groupes de bits, et lequel dispositif de remplissage de zéro remplit les bits de zéro dans au moins certains groupes de la pluralité de groupes de bits, chacun d'entre eux étant constitué d'un même nombre de bits, pour constituer les bits d'information LDPC sur la base d'un schéma de raccourcissement prédéterminé qui est caractérisé en ce que lesdites certains groupes de la pluralité de groupes de bits ne sont pas disposés de manière séquentielle dans les bits d'information LDPC.
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