Processing

Please wait...

Settings

Settings

Goto Application

1. WO2016137255 - PARITY PUNCTURING DEVICE FOR VARIABLE-LENGTH SIGNALING INFORMATION ENCODING, AND PARITY PUNCTURING METHOD USING SAME

Publication Number WO/2016/137255
Publication Date 01.09.2016
International Application No. PCT/KR2016/001879
International Filing Date 25.02.2016
IPC
H03M 13/27 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
27using interleaving techniques
H03M 13/11 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
H03M 13/29 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
29combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
CPC
H03M 13/11
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
H03M 13/27
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
27using interleaving techniques
H03M 13/29
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
29combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
Applicants
  • 한국전자통신연구원 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE [KR]/[KR]
Inventors
  • 박성익 PARK, Sung-Ik
  • 권선형 KWON, Sun-Hyoung
  • 이재영 LEE, Jae-Young
  • 김흥묵 KIM, Heung-Mook
Agents
  • 한양특허법인 HANYANG PATENT FIRM
Priority Data
10-2015-002806527.02.2015KR
10-2016-002084922.02.2016KR
Publication Language Korean (KO)
Filing Language Korean (KO)
Designated States
Title
(EN) PARITY PUNCTURING DEVICE FOR VARIABLE-LENGTH SIGNALING INFORMATION ENCODING, AND PARITY PUNCTURING METHOD USING SAME
(FR) DISPOSITIF DE PERFORATION DE PARITÉ POUR CODAGE D'INFORMATIONS DE SIGNALISATION DE LONGUEUR VARIABLE, ET PROCÉDÉ DE PERFORATION DE PARITÉ L'UTILISANT
(KO) 가변 길이 시그널링 정보 부호화를 위한 패리티 펑처링 장치 및 이를 이용한 패리티 펑처링 방법
Abstract
(EN)
A parity puncturing device and method for variable-length signaling information are disclosed. The parity puncturing device according to one embodiment of the present invention comprises: a memory for providing a parity bit stream for performing parity puncturing on parity bits of an LDPC codeword having a length of 16200 and a code rate of 3/15; and a processor for puncturing bits of the number corresponding to a final puncturing size at the rear of the parity bit stream.
(FR)
L'invention concerne un dispositif et un procédé de perforation de parité pour des informations de signalisation de longueur variable. Le dispositif de perforation de parité selon un mode de réalisation de la présente invention comprend : une mémoire servant à obtenir un train de bits de parité permettant d'exécuter une perforation de parité sur des bits de parité d'un mot de code LDPC ayant une longueur de 16 200 et un rapport de code de 3/15 ; et un processeur servant à perforer des bits du nombre correspondant à une taille de perforation finale à l'arrière du train de bits de parité.
(KO)
가변 길이 시그널링 정보를 위한 패리티 펑처링 장치 및 방법이 개시된다. 본 발명의 일실시예에 따른 패리티 펑처링 장치는, 길이가 16200이고 부호율이 3/15인 LDPC 부호어의 패리티 비트들에 대한 패리티 펑처링을 위한, 패리티 비트열을 제공하는 메모리; 및 상기 패리티 비트열의 뒤쪽에서 최종 펑처링 사이즈에 상응하는 개수의 비트들을 펑처링하는 프로세서를 포함한다.
Latest bibliographic data on file with the International Bureau