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1. WO2016136604 - SEMICONDUCTOR MEMORY DEVICE

Publication Number WO/2016/136604
Publication Date 01.09.2016
International Application No. PCT/JP2016/054809
International Filing Date 19.02.2016
IPC
H01L 27/10 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
CPC
G11C 17/16
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
17Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
14in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
16using electrically-fusible links
H01L 23/5252
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
525with adaptable interconnections
5252comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
H01L 27/11206
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
11206Programmable ROM [PROM], e.g. memory cells comprising a transistor and a fuse or an antifuse
Applicants
  • 株式会社フローディア FLOADIA CORPORATION [JP]/[JP]
Inventors
  • 葛西 秀男 KASAI Hideo
  • 谷口 泰弘 TANIGUCHI Yasuhiro
  • 川嶋 泰彦 KAWASHIMA Yasuhiko
  • 櫻井 良多郎 SAKURAI Ryotaro
  • 品川 裕 SHINAGAWA Yutaka
  • 戸谷 達郎 TOYA Tatsuro
  • 山口 貴徳 YAMAGUCHI Takanori
  • 大和田 福夫 OWADA Fukuo
  • 吉田 信司 YOSHIDA Shinji
  • 畑田 輝男 HATADA Teruo
  • 野田 敏史 NODA Satoshi
  • 加藤 貴文 KATO Takafumi
  • 村谷 哲也 MURAYA Tetsuya
  • 奥山 幸祐 OKUYAMA Kosuke
Agents
  • 吉田 正義 YOSHIDA Tadanori
Priority Data
2015-03585825.02.2015JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR MEMORY DEVICE
(FR) DISPOSITIF DE MÉMOIRE À SEMI-CONDUCTEURS
(JA) 半導体記憶装置
Abstract
(EN)
In this semiconductor memory device (1), without using a conventional control circuit, voltage application from a memory gate electrode (G) to a word line can be shut off by a rectifier element (3) in accordance with a voltage value applied to the memory gate electrode (G) of a memory capacitor (4) and the word line thereof. Hence, conventional switching transistors and a conventional switch control circuit for causing the switching transistors to turn on and off are unnecessary, thereby enabling downsizing. In addition, in the semiconductor memory device (1), four anti-fuse memories (2a6, 2a7, 2a10, 2a11) adjacent to each other share a single bit line contact (BC15), and for example, four anti-fuse memories (2a3, 2a4, 2a7, 2a8) adjacent to each other share a single word line contact (WC12). Hence, in comparison with a case in which an individual bit line contact and an individual word line contact are respectively provided for each anti-fuse memory, downsizing of a whole device can be accomplished.
(FR)
L'invention concerne un dispositif de mémoire à semi-conducteurs (1) dans lequel, sans utiliser un circuit de commande classique, l'application d'une tension d'une électrode de grille de mémoire (G) à une ligne de mots peut être coupée par un élément redresseur (3) en fonction d'une valeur de tension appliquée à l'électrode de grille de mémoire (G) d'un condensateur de mémoire (4) et à sa ligne de mot. De ce fait, des transistors de commutation classiques et un circuit de commande de commutateur classique pour provoquer le blocage et le déblocage des transistors de commutation sont inutiles, ce qui permet une miniaturisation. De plus, dans le dispositif de mémoire à semi-conducteurs (1), quatre mémoires anti-fusibles (2a6, 2a7, 2a10, 2a11) adjacentes l'une à l'autre partagent un seul contact de ligne de bit (BC15), et par exemple, quatre mémoires anti-fusibles (2a3, 2a4, 2a7, 2a8) adjacentes l'une à l'autre partagent un seul contact de ligne de mot (WC12). Par conséquent, par comparaison à un cas dans lequel un contact de ligne de bit individuel et un contact de ligne de mot individuel sont prévus respectivement pour chaque mémoire anti-fusible, une miniaturisation d'un dispositif entier peut être réalisée.
(JA)
半導体記憶装置(1)では、従来のような制御回路を用いずに、メモリキャパシタ(4)のメモリゲート電極(G)およびワード線へ印加される電圧値によって整流素子(3)によりメモリゲート電極(G)からワード線への電圧印加を遮断でき、かくして、従来のようなスイッチトランジスタや、さらにスイッチトランジスタにオンオフ動作を行わせるためのスイッチ制御回路が不要になり、その分、小型化を図り得る。また、半導体記憶装置(1)では、互いに隣接する4 個のアンチヒューズメモリ(2a6,2a7,2a10,2a11)で1 個のビット線コンタクト(BC15)を共有するとともに、例えば互いに隣接する4 個のアンチヒューズメモリ(2a3,2a4,2a7,2a8)で1 個のワード線コンタクト(WC12)を共有するようにしたことにより、各アンチヒューズメモリ毎にビット線コンタクトおよびワード線コンタクトをそれぞれ個別に設ける場合に比して装置全体として小型化を図り得る。
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