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1. WO2016135744 - A SYSTEM AND METHOD FOR MULTI-CYCLE WRITE LEVELING

Publication Number WO/2016/135744
Publication Date 01.09.2016
International Application No. PCT/IN2016/000048
International Filing Date 24.02.2016
IPC
G11C 7/22 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
22Read-write timing or clocking circuits; Read-write control signal generators or management
G11C 11/40 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
CPC
G11C 11/4076
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4076Timing circuits
G11C 11/4096
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
G11C 2207/2254
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
22Control and timing of internal memory operations
2254Calibration
G11C 29/023
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
023in clock generator or timing circuitry
G11C 5/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
04Supports for storage elements ; , e.g. memory modules; Mounting or fixing of storage elements on such supports
G11C 8/18
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Applicants
  • GYAN, Prakash [IN]/[IN]
  • NIDHIR, Kumar [IN]/[IN]
Inventors
  • GYAN, Prakash
  • NIDHIR, Kumar
Agents
  • PRABHU, Rakesh
Priority Data
892/CHE/201525.02.2015IN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) A SYSTEM AND METHOD FOR MULTI-CYCLE WRITE LEVELING
(FR) SYSTÈME ET PROCÉDÉ DE MISE À NIVEAU D'ÉCRITURE À CYCLES MULTIPLES
Abstract
(EN)
A method and system for multi cycle write leveling are disclosed. At least three data patterns are written into consecutive address locations of a memory device via corresponding write operations. Subsequently, predetermined beats of data strobe signals corresponding to certain predetermined write operations are gated. Based at least on the gating of predetermined data beats, a target data pattern to be read from the memory device is determined. Subsequently, a data read operation is performed, and the data written onto a specific address location of the memory device is read there from. The data thus read from the memory device is compared with the target pattern. Based on the comparison of the data read from the memory device with the target pattern, a delay cycle between the data strobe signals and clock signal is determined, and the data strobe signal and clock signal are accordingly calibrated.
(FR)
L'invention concerne un système et un procédé de mise à niveau d'écriture à cycles multiples. Au moins trois motifs de données sont écrits à des emplacements d'adresse consécutifs d'un dispositif de mémoire via des opérations d'écriture correspondantes. Ensuite, des battements prédéterminés de signaux d'échantillonnage de données correspondant à certaines opérations d'écriture prédéterminées sont pointés. D'après le pointage de battements de données prédéterminés, un motif de données cible devant être lu à partir du dispositif de mémoire est déterminé. Ensuite, une opération de lecture de données est exécutée, et les données écrites à un emplacement d'adresse spécifique du dispositif de mémoire sont lues à partir de là. Les données ainsi lues à partir du dispositif de mémoire sont comparées au motif cible. D'après le résultat de la comparaison entre les données lues à partir du dispositif de mémoire et le motif cible, un cycle de retard entre les signaux d'échantillonnage de données et un signal d'horloge est déterminé, et le signal d'échantillonnage de données et le signal d'horloge sont étalonnés en conséquence.
Also published as
Latest bibliographic data on file with the International Bureau