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1. WO2016135591 - MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM

Publication Number WO/2016/135591
Publication Date 01.09.2016
International Application No. PCT/IB2016/050865
International Filing Date 18.02.2016
IPC
G06F 12/16 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
16Protection against loss of memory contents
CPC
G06F 11/106
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1048using arrangements adapted for a specific error detection or correction feature
106Correcting systematically all correctable errors, i.e. scrubbing
G06F 11/1068
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1068in sector programmable memories, e.g. flash disk
G11C 29/52
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
Applicants
  • SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP]/[JP]
Inventors
  • TSUTSUI, Naoaki
Priority Data
2015-03676826.02.2015JP
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM
(FR) SYSTÈME DE MÉMOIRE ET SYSTÈME DE TRAITEMENT D'INFORMATIONS
Abstract
(EN)
A memory system that includes an error check and correct (ECC) circuit is provided. The memory system includes a memory, the ECC circuit, and a processor. The processor controls the entire operation of the memory system. The memory includes a user data region and a management region. The management region stores access information of each of blocks in the user data region as a management table. The value of the access information is either a first value indicating that the number of access times is 0 or a second value indicating that the number of access times is greater than or equal to 1. When the value of the access information of the block is the first value, the circuit checks and corrects an error of data read from the block. When the value of the access information of the block is the second value, the circuit does not check and correct an error of data read from the block.
(FR)
L'invention concerne un système de mémoire qui comprend un circuit de vérification et de correction d'erreur (ECC). Le système de mémoire comprend une mémoire, le circuit ECC, et un processeur. Le processeur commande tout le fonctionnement du système de mémoire. La mémoire comprend une région de données d'utilisateur et une région de gestion. La région de gestion stocke des informations d'accès de chacun des blocs dans la région de données d'utilisateur sous la forme d'une table de gestion. La valeur des informations d'accès est soit une première valeur indiquant que le nombre d'accès est 0 ou une deuxième valeur indiquant que le nombre d'accès est supérieur ou égal à 1. Lorsque la valeur des informations d'accès du bloc est la première valeur, le circuit vérifie et corrige une erreur de données lues à partir du bloc. Lorsque la valeur des informations d'accès du bloc est la deuxième valeur, le circuit ne vérifie pas et ne corrige pas une erreur de données lues à partir du bloc.
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