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1. (WO2016105211) A METHOD OF EPITAXIAL GROWTH OF A MATERIAL INTERFACE BETWEEN GROUP III-V MATERIALS AND SILICON WAFERS PROVIDING COUNTERBALANCING OF RESIDUAL STRAINS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2016/105211    International Application No.:    PCT/NO2015/050261
Publication Date: 30.06.2016 International Filing Date: 23.12.2015
Chapter 2 Demand Filed:    03.10.2016    
IPC:
H01L 21/02 (2006.01), H01L 31/0304 (2006.01), H01L 31/18 (2006.01)
Applicants: INTEGRATED SOLAR [NO/NO]; Osloveien 23 7018 Trondheim (NO)
Inventors: BUGGE, Renato; (NO).
MYRVÅGNES, Geir; (NO)
Agent: BRYN AARFLOT AS; Stortingsgata 8 P.O. Box 449 Sentrum N-0104 Oslo (NO)
Priority Data:
14200021.5 23.12.2014 EP
Title (EN) A METHOD OF EPITAXIAL GROWTH OF A MATERIAL INTERFACE BETWEEN GROUP III-V MATERIALS AND SILICON WAFERS PROVIDING COUNTERBALANCING OF RESIDUAL STRAINS
(FR) PROCÉDÉ DE CROISSANCE ÉPITAXIALE D'UNE INTERFACE DE MATÉRIAUX ENTRE DES MATÉRIAUX DES GROUPES III À V ET DES TRANCHES DE SILICIUM ASSURANT LE CONTREBALANCEMENT DES CONTRAINTES RÉSIDUELLES
Abstract: front page image
(EN)The present invention relates to a method of manufacturing semiconductor materials comprising interface layers of group III-V materials in combination with Si substrates. Especially the present invention is related to a method of manufacturing semiconductor materials comprising GaAs in combination with Si(111) substrates, wherein residual strain due to different thermal expansion coefficient of respective materials is counteracted by introducing added layer(s) compensating the residual strain.
(FR)La présente invention concerne un procédé de fabrication de matériaux semi-conducteurs comportant des couches d'interface de matériaux des groupes III à V en combinaison avec des substrats en Si. En particulier, la présente invention concerne un procédé de fabrication de matériaux semi-conducteurs comportant du GaAs en combinaison avec des substrats en Si(lll), la contrainte résiduelle due à des coefficients de dilatation thermique différents de matériaux respectifs étant contrebalancée en introduisant une ou des couches supplémentaires compensant la contrainte résiduelle.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)