WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2016101632) METHOD FOR MANUFACTURING THIN FILM TRANSISTOR AND RELATED ACTIVE LAYER FOR THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2016/101632    International Application No.:    PCT/CN2015/087016
Publication Date: 30.06.2016 International Filing Date: 14.08.2015
IPC:
H01L 29/786 (2006.01), H01L 21/84 (2006.01), H01L 27/12 (2006.01)
Applicants: BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015 (CN)
Inventors: WANG, Zuqiang; (CN).
LIU, Chien Hung; (CN).
CHAN, Yucheng; (CN).
HUANGFU, Lujiang; (CN)
Agent: TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS; CHEN, Yuan 10th Floor, Tower D, Minsheng Financial Center 28 Jianguomennei Avenue, Dongcheng District Beijing 100005 (CN)
Priority Data:
201410815652.0 23.12.2014 CN
Title (EN) METHOD FOR MANUFACTURING THIN FILM TRANSISTOR AND RELATED ACTIVE LAYER FOR THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS
(FR) PROCÉDÉ DE FABRICATION D'UN TRANSISTOR À FILM MINCE ET COUCHE ACTIVE CONNEXE POUR TRANSISTOR À FILM MINCE, TRANSISTOR À FILM MINCE, SUBSTRAT DE RÉSEAU ET APPAREIL D'AFFICHAGE
Abstract: front page image
(EN)A method for forming an active layer (3) with a pattern is provided. The method includes forming an amorphous silicon layer (31) and forming a function layer (4) on the amorphous silicon layer (31). The function layer (4) has a same pattern as the active layer (3). The method further includes performing a crystallization process for converting the amorphous silicon layer (31) to a poly-silicon layer (32). The poly-silicon layer (32) has first portions covered by the function layer (4) and second portions not covered by the function layer (4), and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.
(FR)L'invention concerne un procédé de formation d'une couche active (3) pourvue d'un motif. Le procédé consiste à former une couche de silicium amorphe (31) et une couche de fonction (4) sur la couche de silicium amorphe (31). La couche de fonction (4) présente le même motif que la couche active (3). Le procédé consiste également à effectuer un processus de cristallisation pour convertir la couche de silicium amorphe (31) en une couche de polysilicium (32). La couche de polysilicium (32) comporte des premières parties recouvertes par la couche de fonction (4) et des secondes parties qui ne sont pas recouvertes par la couche de fonction (4), et la granulométrie du polysilicium dans les premières parties est supérieure à celle des secondes parties.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)