Search International and National Patent Collections

1. (WO2016064513) BOTTOM RECESS PROCESS FOR AN OUTER BLOCKING DIELECTRIC LAYER INSIDE A MEMORY OPENING

Pub. No.:    WO/2016/064513    International Application No.:    PCT/US2015/051331
Publication Date: Fri Apr 29 01:59:59 CEST 2016 International Filing Date: Wed Sep 23 01:59:59 CEST 2015
IPC: H01L 21/28
H01L 27/115
Applicants: SANDISK TECHNOLOGIES LLC
Inventors: TSUTSUMI, Masanori
SASAKI, Hiroshi
OGAWA, Hiroyuki
SANO, Michiaki
MIYAMOTO, Masato
YAMAGUCHI, Kensuke
SHIMABUKURO, Seiji
Title: BOTTOM RECESS PROCESS FOR AN OUTER BLOCKING DIELECTRIC LAYER INSIDE A MEMORY OPENING
Abstract:
A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer (501) is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers (32, 42). A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate (10) can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer (503) can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.