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Machine translation
1. (WO2016064004) METHOD FOR PREPARING INTEGRATED CIRCUIT DEVICE PACKAGE
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2016/064004 International Application No.: PCT/KR2014/009989
Publication Date: 28.04.2016 International Filing Date: 23.10.2014
IPC:
H01L 23/12 (2006.01) ,H01L 27/12 (2006.01) ,H01L 21/306 (2006.01) ,H01L 21/3065 (2006.01)
Applicants: HANA MICRON INC.[KR/KR]; 77, Yeonamyulgeum-ro, Eumbong-myeon Asan-si Chungcheongnam-do 336-864, KR
Inventors: LIM, Jae-sung; KR
Agent: HWANG MOK PARK IP GROUP; KR
Priority Data:
Title (EN) METHOD FOR PREPARING INTEGRATED CIRCUIT DEVICE PACKAGE
(FR) PROCÉDÉ DE PRÉPARATION DE BOÎTIER DE DISPOSITIF À CIRCUIT INTÉGRÉ
(KO) 집적회로 소자 패키지의 제조 방법
Abstract: front page image
(EN) A method for preparing an integrated circuit device package can comprise the steps of: preparing a silicon-on-insulator (SOI) substrate which has sequentially laminated from the bottom a second silicon substrate, an insulating film, and a first silicon substrate that has a flexible thickness so as to be bent or folded; forming a circuit pattern on one side of the first silicon substrate; separating the first silicon substrate and the second silicon substrate from each other by removing the insulating film by means of etching on the insulating film; and adhering a lower substrate, which is formed from a flexible material and has a flexible thickness so as to be bent or folded, on the other side of the first silicon substrate which is opposite from the one side of the first silicon substrate having the circuit pattern formed thereon.
(FR) L'invention porte sur un procédé de préparation d'un boîtier de dispositif à circuit intégré qui peut comprendre les étapes consistant : à préparer un substrat silicium sur isolant (SOI) qui comprend, séquentiellement stratifiés à partir du bas, un second substrat en silicium, un film isolant, et un premier substrat en silicium qui présente une épaisseur souple de manière à être courbé ou plié ; à former un motif de circuit sur un côté du premier substrat en silicium ; à séparer le premier substrat en silicium et le second substrat en silicium l'un de l'autre par élimination du film isolant au moyen d'une gravure sur le film isolant ; et à coller un substrat inférieur, qui est formé à partir d'un matériau souple et présente une épaisseur souple de manière à être courbé ou plié, sur l'autre côté du premier substrat en silicium qui est à l'opposé dudit côté du premier substrat en silicium sur lequel est formé le motif de circuit.
(KO) 집적회로 소자 패키지의 제조 방법은 아래로부터 제2 실리콘 기판, 절연막, 및 휘거나 접을 수 있는 유연한 두께를 갖는 제1 실리콘 기판이 순차적으로 적층되는 에스오아이(SOI : silicon on insulator) 기판을 마련하는 단계; 상기 제1 실리콘 기판의 일면에 회로 패턴을 형성하는 단계; 상기 절연막을 대상으로 식각 공정을 수행하여 상기 절연막을 제거하여 상기 제1 실리콘 기판과 상기 제2 실리콘 기판을 서로 분리시키는 단계; 및 상기 회로 패턴이 형성되는 상기 제1 실리콘 기판의 일면과 반대되는 상기 제1 실리콘 기판의 타면에 휘거나 접을 수 있는 유연한 두께 및 유연한 재질로 이루어지는 하부 기판을 부착시키는 단계를 포함할 수 있다.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Korean (KO)
Filing Language: Korean (KO)