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1. (WO2016061855) TFT ARRAY SUBSTRATE

Pub. No.:    WO/2016/061855    International Application No.:    PCT/CN2014/090459
Publication Date: Fri Apr 29 01:59:59 CEST 2016 International Filing Date: Fri Nov 07 00:59:59 CET 2014
IPC: G02F 1/1362
G09G 3/36
Applicants: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO.,LTD.
深圳市华星光电技术有限公司
Inventors: CHEN, Caiqin
陈彩琴
Title: TFT ARRAY SUBSTRATE
Abstract:
Provided is a TFT array substrate, the display area (A) whereof comprises a plurality of data lines (D1, D2, D3, D4, D5), a plurality of scan lines (G1, G2, G3, G4, G5, G6, G7, G8), and subpixels layed out in an array; in a single row of subpixels, a row of odd subpixels and a row of even subpixels arranged to the left and the right of each data line (D1, D2, D3, D4, D5) are connected separately to said data lines (D1, D2, D3, D4, D5) by means of a common TFT power line; in a single row of subpixels, the row of even subpixels is electrically connected to a scan line located above said row of subpixels, and the row of odd subpixels is electrically connected to a scan line located below said row of subpixels; the non-display area (B) comprises a plurality of fanout lines (Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8), each such fanout line (Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8) being connected to a corresponding scan line, and each such fanout line (Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8) comprising a straight-line area and a slanted-line area; the slanted-line areas of the two fanout lines of the two corresponding upper and lower adjacent scan lines to which each second or fourth successively-arranged scan line is respectively connected insulatedly cross over one another, thus changing the drive sequence of said two upper and lower adjacent scan lines.