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1. (WO2016060753) MULTI-LAYER DIELECTRIC STACK FOR PLASMA DAMAGE PROTECTION
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2016/060753 International Application No.: PCT/US2015/048956
Publication Date: 21.04.2016 International Filing Date: 08.09.2015
IPC:
H01L 21/31 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
Applicants: APPLIED MATERIALS, INC.[US/US]; 3050 Bowers Avenue Santa Clara, California 95054, US
Inventors: XIE, Bo; US
YIM, Kang Sub; US
PAN, Cheng; US
NGO, Sure; US
KIM, Taewan; US
DEMOS, Alexandros T.; US
Agent: PATTERSON, B. Todd; US
Priority Data:
62/064,39615.10.2014US
Title (EN) MULTI-LAYER DIELECTRIC STACK FOR PLASMA DAMAGE PROTECTION
(FR) EMPILEMENT DIÉLECTRIQUE MULTICOUCHE POUR UNE PROTECTION CONTRE LES DOMMAGES DUS AU PLASMA
Abstract:
(EN) Embodiments of the disclosure generally provide multi-layer dielectric stack configurations that are resistant to plasma damage. Methods are disclosed for the deposition of thin protective low dielectric constant layers upon bulk low dielectric constant layers to create the layer stack. As a result, the dielectric constant of the multi-layer stack is unchanged during and after plasma processing.
(FR) Des modes de réalisation de l'invention concernent, d'une manière générale, des configurations d'empilement diélectrique multicouche qui sont résistantes aux dommages dus au plasma. L'invention concerne des procédés de dépôt de couches minces de protection à faible constante diélectrique sur des couches en vrac à faible constante diélectrique pour créer l'empilement de couches. En conséquence, la constante diélectrique de l'empilement multicouche est inchangée pendant et après le traitement au plasma.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)