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1. (WO2016058055) TRAINABLE ANALOGUE BLOCK
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2016/058055 International Application No.: PCT/AU2015/050638
Publication Date: 21.04.2016 International Filing Date: 16.10.2015
IPC:
G06N 3/08 (2006.01) ,G06N 3/02 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
08
Learning methods
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
N
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3
Computer systems based on biological models
02
using neural network models
Applicants: WESTERN SYDNEY UNIVERSITY[AU/AU]; C/- UWS Research Engagement, Development and Innovation, Locked Bag 1797 Penrith, New South Wales 2751, AU
Inventors: SCHAIK, Floris André Van; AU
HAMILTON, Tara Julia; AU
TAPSON, Jonathon Craig; AU
THAKUR, Chetan Singh; AU
Agent: FB RICE; Level 23, 44 Market St Sydney, New South Wales 2000, AU
Priority Data:
201490415417.10.2014AU
Title (EN) TRAINABLE ANALOGUE BLOCK
(FR) BLOC ANALOGIQUE À CAPACITÉ D'APPRENTISSAGE
Abstract:
(EN) A trainable analogue circuit block (TAB) (10) includes an input layer (12) defining at least one input node (14). At least one hidden layer (16) defines at least one hidden node (20). A non-linear circuit connects the at least one hidden layer (16) to the input layer (12), the non-linear circuit comprising at least one non-linear weight (18). An output layer (22) defines at least one output node (24), the output layer (22) being connected to the at least one hidden layer (20) via at least one trainable weight (26).
(FR) L’invention concerne un bloc de circuit analogique à capacité d'apprentissage (TAB) (10) qui comprend une couche d’entrée (12) définissant au moins un nœud d’entrée (14). Au moins une couche cachée (16) définit au moins un nœud caché (20). Un circuit non linéaire connecte la ou les couches cachées (16) à la couche d’entrée (12), le circuit non linéaire comprenant au moins un poids non linéaire (18). Une couche de sortie (22) définit au moins un nœud de sortie (24), la couche de sortie (22) étant connectée à ladite couche cachée (20) par l’intermédiaire d’au moins un poids à capacité d'apprentissage (26).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)