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1. (WO2016051599) MEMORY CONTROLLER AND DATA CONTROL METHOD

Pub. No.:    WO/2016/051599    International Application No.:    PCT/JP2014/076592
Publication Date: Fri Apr 08 01:59:59 CEST 2016 International Filing Date: Sat Oct 04 01:59:59 CEST 2014
IPC: G06F 12/16
Applicants: HITACHI, LTD.
株式会社日立製作所
Inventors: MIZUSHIMA, Nagamasa
水島 永雅
KAWAMURA, Atsushi
河村 篤志
KOSEKI, Hideyuki
小関 英通
Title: MEMORY CONTROLLER AND DATA CONTROL METHOD
Abstract:
This memory controller comprises an error checking and correcting circuit which performs a calculation regarding data error correction code, and a processor which, by using the error checking and correcting circuit, writes an error correction code associated with data to a nonvolatile memory when writing the data to the nonvolatile memory, and performs error correction on the data using the error correction code when reading the data from the nonvolatile memory. The processor counts the number of erroneous bits in the data stored in each block, which is a bulk erase unit of data, and stores a first error correction code, which has a predetermined error correction capability for the data, in the block together with the data if the number of erroneous bits does not exceed a predetermined reference value, or stores a second error correction code, which has a higher error correction capability for the data than the first error correction code, in the block together with the data if the number of erroneous bits exceeds the predetermined reference value.