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1. WO2016036491 - SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

Publication Number WO/2016/036491
Publication Date 10.03.2016
International Application No. PCT/US2015/045169
International Filing Date 14.08.2015
IPC
H04L 9/06 2006.1
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
9Arrangements for secret or secure communication
06the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
CPC
G06F 21/72
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
71to assure secure computing or processing of information
72in cryptographic circuits
G06F 9/30007
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
G06F 9/3001
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
3001Arithmetic instructions
G06F 9/30018
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
30018Bit or string instructions; instructions using a mask
G06F 9/30036
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30003Arrangements for executing specific machine instructions
30007to perform operations on data operands
30036Instructions to perform operations on packed data, e.g. vector operations
G06F 9/3016
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
30145Instruction analysis, e.g. decoding, instruction word fields
3016Decoding the operand specifier, e.g. specifier format
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • GUERON, Shay
  • KRASNOV, Vlad
Agents
  • VECCHIA, Brent E.
Priority Data
14/477,55204.09.2014US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
(FR) PROCESSEURS, PROCÉDÉS, SYSTÈMES ET INSTRUCTIONS D'ACCÉLÉRATION D'ALGORITHME DE HACHAGE EN SM3
Abstract
(EN)
A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.
(FR)
L'invention concerne un processeur qui inclut une unité de décodage pour décoder une instruction d'actualisation de mot d'état en deux tours en SM3. L'instruction sert à indiquer un ou plusieurs opérandes de données en paquets sources. L'opérande ou les opérandes de données en paquets sources doivent comporter huit mots d'état de 32 bits (Aj, Bj, Cj, Dj, Ej, Fj, Gj, et Hj) qui doivent correspondre à un tour (j) d'un algorithme de hachage en SM3. L'opérande ou les opérandes de données de paquets sources doivent également comporter un ensemble de messages suffisants pour évaluer deux tours de l'algorithme de hachage en SM3. Une unité d'exécution couplée à l'unité de décodage peut fonctionner, en réponse à une instruction, pour enregistrer un ou plusieurs opérandes de données en paquets de résultats, dans un ou plusieurs emplacements d'enregistrement de destination. L'opérande ou les opérandes de données en paquets de résultats doivent comporter au moins quatre mots d'état de 32 bits en deux tours (Aj+2, Bj+2, Ej+2, et Fj+2), lesquels doivent correspondre à un tour (j+2) de l'algorithme de hachage en SM3.
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