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1. WO2015183581 - METHOD AND SYSTEM FOR DYNAMIC WORD LINE BASED CONFIGURATION OF A THREE-DIMENSIONAL MEMORY DEVICE

Publication Number WO/2015/183581
Publication Date 03.12.2015
International Application No. PCT/US2015/030851
International Filing Date 14.05.2015
IPC
G11C 16/34 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 16/04 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
G11C 11/56 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/10 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
G11C 13/00 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
CPC
G06F 11/1072
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1072in multilevel memories
G11C 11/5628
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
5621using charge storage in a floating gate
5628Programming or writing circuits; Data input circuits
G11C 13/0002
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
G11C 16/0483
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
04using variable threshold transistors, e.g. FAMOS
0483comprising cells having several storage transistors connected in series
G11C 16/10
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
10Programming or data input circuits
G11C 16/3404
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
Applicants
  • SANDISK TECHNOLOGIES LLC [US]/[US]
Inventors
  • HIGGINS, James, M.
  • ELLIS, Robert, W.
  • DARRAGH, Neil, R.
  • OLBRICH, Aaron, K.
  • KANKANI, Navneeth
  • SPROUSE, Steven
Agents
  • WILLIAMS, Gary, S.
Priority Data
14/298,84106.06.2014US
62/005,93030.05.2014US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) METHOD AND SYSTEM FOR DYNAMIC WORD LINE BASED CONFIGURATION OF A THREE-DIMENSIONAL MEMORY DEVICE
(FR) PROCÉDÉ ET SYSTÈME POUR UNE CONFIGURATION DYNAMIQUE BASÉE SUR UNE LIGNE DE MOTS D'UN DISPOSITIF DE MÉMOIRE TRIDIMENSIONNELLE
Abstract
(EN) A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.
(FR) Selon l'invention, un dispositif de commande de mémoire configure une pluralité de lignes de mots associées à un bloc respectif d'un dispositif de mémoire tridimensionnelle (3D) dans une première configuration, la première configuration comprenant un ensemble de paramètres de configuration pour chaque ligne de mots de la pluralité de lignes de mots déterminés au moins en partie sur les positions verticales de chaque ligne de mots par rapport à un substrat du dispositif de mémoire 3D et, tandis que la pluralité de lignes de mots sont configurées dans la première configuration, écrit des données dans le bloc respectif et lit des données à partir du bloc respectif. Pour le bloc respectif, le dispositif de commande de mémoire : règle un premier paramètre dans l'ensemble respectif de paramètres de configuration correspondant à une ligne de mots respective de la pluralité de lignes de mots en réponse à la détection d'une première condition de déclenchement quant à la ligne de mots respective et, après réglage du premier paramètre, écrit des données dans la ligne de mots respective et lit des données à partir de la ligne de mots respective.
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