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1. WO2015179215 - CLOCK DISTRIBUTION ARCHITECTURE FOR LOGIC TILES OF AN INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF

Publication Number WO/2015/179215
Publication Date 26.11.2015
International Application No. PCT/US2015/030912
International Filing Date 14.05.2015
IPC
G06F 1/10 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
10Distribution of clock signals
H03K 19/177 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
CPC
G06F 1/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
08Clock generators with changeable or programmable clock frequency
G06F 1/10
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
10Distribution of clock signals ; , e.g. skew
H03K 19/17724
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17724Structural details of logic blocks
H03K 19/1774
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17736Structural details of routing resources
1774for global signals, e.g. clock, reset
H03K 19/17744
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17736Structural details of routing resources
17744for input/output signals
H03K 19/17748
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
19Logic circuits, i.e. having at least two inputs acting on one output
02using specified components
173using elementary logic circuits as components
177arranged in matrix form
17748Structural details of configuration resources
Applicants
  • FLEX LOGIX TECHNOLOGIES, INC. [US]/[US]
Inventors
  • WANG, Cheng, C.
Agents
  • STEINBERG, Neil
Priority Data
62/000,36119.05.2014US
62/114,55810.02.2015US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) CLOCK DISTRIBUTION ARCHITECTURE FOR LOGIC TILES OF AN INTEGRATED CIRCUIT AND METHOD OF OPERATION THEREOF
(FR) ARCHITECTURE DE DISTRIBUTION D'HORLOGE POUR BLOCS LOGIQUES DE CIRCUIT INTÉGRÉ ET SON PROCÉDÉ DE FONCTIONNEMENT
Abstract
(EN) An integrated circuit includes a plurality of logic tiles, wherein each logic tile includes a plurality of edges and is configurable to connect with adjacent logic tile. Each logic tile includes a plurality of input/output clock paths, wherein each input/output clock path is associated with a different edge of the logic tile. The plurality of input/output clock paths include a plurality of input clock path, each input clock path configurable to receive a tile input clock signal from an adjacent first logic tile, and a plurality of output clock paths, each output clock path configurable to output a tile output clock signal to an adjacent second logic tile. An output clock path includes a u-turn circuit to receive a tile clock signal having a first predetermined skew and provide a tile clock signal having a second predetermined skew.
(FR) Un circuit intégré comprend une pluralité de blocs logiques. Chaque bloc logique comporte une pluralité de bords et peut être conçu pour se connecter à un bloc logique adjacent. Chaque bloc logique comporte une pluralité de chemins d'horloge d'entrée/sortie. Chaque chemin d'horloge d'entrée/sortie est associé à un bord différent du bloc logique. La pluralité de chemins d'horloge d'entrée/sortie comprend une pluralité de chemins d'horloge d'entrée, chaque chemin d'horloge d'entrée pouvant être conçu pour recevoir un signal d'horloge d'entrée de bloc provenant d'un premier bloc logique adjacent, et une pluralité de chemins d'horloge de sortie, chaque chemin d'horloge de sortie pouvant être conçu pour sortir un signal d'horloge de sortie de bloc à destination d'un second bloc logique adjacent. Un chemin d'horloge de sortie comprend un circuit de demi-tour destiné à recevoir un signal d'horloge de bloc ayant un premier décalage prédéterminé et à émettre un signal d'horloge de bloc ayant un second décalage prédéterminé.
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