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1. WO2015138058 - PIEZOELECTRIC AND LOGIC INTEGRATED DELAY LINE MEMORY

Publication Number WO/2015/138058
Publication Date 17.09.2015
International Application No. PCT/US2015/014324
International Filing Date 03.02.2015
IPC
G11C 21/02 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
21Digital stores in which the information circulates
02using electromechanical delay lines, e.g. using a mercury tank
CPC
B06B 1/0215
BPERFORMING OPERATIONS; TRANSPORTING
06GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
BMETHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, ; e.g.; FOR PERFORMING MECHANICAL WORK IN GENERAL
1Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
02making use of electrical energy
0207Driving circuits
0215for generating pulses, e.g. bursts of oscillations, envelopes
B06B 2201/20
BPERFORMING OPERATIONS; TRANSPORTING
06GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
BMETHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, ; e.g.; FOR PERFORMING MECHANICAL WORK IN GENERAL
2201Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
20Application to multi-element transducer
B06B 2201/55
BPERFORMING OPERATIONS; TRANSPORTING
06GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
BMETHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, ; e.g.; FOR PERFORMING MECHANICAL WORK IN GENERAL
2201Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
50Application to a particular transducer type
55Piezoelectric transducer
B06B 2201/70
BPERFORMING OPERATIONS; TRANSPORTING
06GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
BMETHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, ; e.g.; FOR PERFORMING MECHANICAL WORK IN GENERAL
2201Indexing scheme associated with B06B1/0207 for details covered by B06B1/0207 but not provided for in any of its subgroups
70Specific application
G11C 19/00
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
19Digital stores in which the information is moved stepwise, e.g. shift register
G11C 2013/0095
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
0002using resistive RAM [RRAM] elements
0021Auxiliary circuits
0069Writing or programming circuits or methods
0095Write using strain induced by, e.g. piezoelectric, thermal effects
Applicants
  • CORNELL UNIVERSITY [US]/[US]
Inventors
  • LAL, Amit
  • KUO, Justin, C.
Agents
  • AI, Bing
Priority Data
61/935,31003.02.2014US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) PIEZOELECTRIC AND LOGIC INTEGRATED DELAY LINE MEMORY
(FR) MÉMOIRE À LIGNE À RETARD À LOGIQUE INTÉGRÉE ET PIÉZO-ÉLECTRIQUE
Abstract
(EN) Delay line memory device, systems and methods are disclosed. In one aspect, a delay line memory device includes a substrate; an electronic unit disposed on the substrate and operable to receive, amplify, and/or synchronize data signals into a bit stream to be transmitted as acoustic pulses carrying data stored in the delay line memory device; a first and a second piezoelectric transducer disposed on the substrate and in communication with the electronic unit, in which the first piezoelectric transducer is operable to transmit the data signals to the acoustic pulses that carry the data through the bulk of the substrate, and the second piezoelectric transducer is operable to transduce the received acoustic pulses to intermediate electrical signals containing the data, which are transferred to the electronic unit via an electrical interconnect to cause refresh of the data in the delay line memory device.
(FR) L'invention concerne un dispositif de mémoire à ligne de retard, ainsi que des systèmes et des procédés associés. Selon un aspect de l'invention, ce dispositif de mémoire à ligne à retard comprend un substrat; une unité électronique disposée sur le substrat et permettant de recevoir, amplifier et/ou synchroniser des signaux de données dans un flux binaire à transmettre en tant qu'impulsions acoustiques transportant des données stockées dans le dispositif de mémoire à ligne à retard; un premier et un deuxième transducteur piézo-électrique disposés sur le substrat et en communication avec l'unité électronique, le premier transducteur piézoélectrique permettant de transmettre les signaux de données aux impulsions acoustiques qui transportent les données à travers la majeure partie du substrat, et le deuxième transducteur piézoélectrique permettant de convertir les impulsions acoustiques reçues en signaux électriques intermédiaires contenant les données, qui sont transférées à l'unité électronique par l'intermédiaire d'une interconnexion électrique pour provoquer un rafraîchissement des données dans le dispositif de mémoire à ligne à retard.
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