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1. WO2015133728 - SOLDER BUMP STRUCTURE AND MANUFACTURING METHOD THEREFOR

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Publication Number WO/2015/133728
Publication Date 11.09.2015
International Application No. PCT/KR2015/000818
International Filing Date 27.01.2015
IPC
H01L 23/48 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/60 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/12 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
12Mountings, e.g. non-detachable insulating substrates
CPC
H01L 21/60
H01L 2224/05166
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
05001Internal layers
05099Material
051with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05163the principal constituent melting at a temperature of greater than 1550°C
05166Titanium [Ti] as principal constituent
H01L 2224/05624
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05617the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
05624Aluminium [Al] as principal constituent
H01L 2224/05647
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
02Bonding areas; Manufacturing methods related thereto
04Structure, shape, material or disposition of the bonding areas prior to the connecting process
05of an individual bonding area
0554External layer
05599Material
056with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
05638the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
05647Copper [Cu] as principal constituent
H01L 2224/11
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
11Manufacturing methods
H01L 2224/1145
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
10Bump connectors; Manufacturing methods related thereto
11Manufacturing methods
114by blanket deposition of the material of the bump connector
11444in gaseous form
1145Physical vapour deposition [PVD], e.g. evaporation, or sputtering
Applicants
  • 서울대학교 산학협력단 SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION [KR]/[KR]
Inventors
  • 이정중 LEE, Jungjoong
  • 최한주 CHOE, Hanjoo
  • 권순호 KWON, Soonho
Agents
  • 이인행 LEE, InHaeng
Priority Data
10-2014-002676806.03.2014KR
Publication Language Korean (ko)
Filing Language Korean (KO)
Designated States
Title
(EN) SOLDER BUMP STRUCTURE AND MANUFACTURING METHOD THEREFOR
(FR) STRUCTURE DE BOSSAGE DE SOUDURE ET SON PROCÉDÉ DE FABRICATION
(KO) 솔더 범프 구조체 및 그 제조방법
front page image
Abstract
(EN) The present invention provides a manufacturing method for a solder bump structure, and a solder bump structure implemented by the manufacturing method. The manufacturing method comprises the steps of: preparing a device having a conductive pad formed thereon; forming an insulation layer on the conductive pad and on at least a portion of the device; forming an insulation layer pattern having a cavity for exposing the conductive pad by making the insulation layer subjected to etching; forming a solder layer on the conductive pad and on the front surface on the insulation layer pattern; forming a solder bump making direct contact with the conductive pad which is surrounded by the insulation layer pattern, by making the solder layer subjected to dewetting through plasma; and removing the insulation layer pattern.
(FR) La présente invention porte sur un procédé de fabrication pour une structure de bossage de soudure, et sur une structure de bossage de soudure mise en œuvre par le procédé de fabrication. Le procédé de fabrication comprend les étapes suivantes : la préparation d'un dispositif ayant une plot conducteur formé sur ce dernier ; la formation d'une couche d'isolation sur le plot conducteur et sur au moins une partie du dispositif ; la formation d'un motif de couche d'isolation ayant une cavité pour présenter le plot conducteur soumettant la couche d'isolation à une gravure ; la formation d'une couche de soudure sur le plot conducteur et sur la surface avant sur le motif de couche d'isolation ; la formation d'un bossage de soudure établissant un contact direct avec le plot conducteur qui est entouré par le motif de couche d'isolation, soumettant la couche de soudure à un démouillage par plasma ; et le retrait du motif de couche d'isolation.
(KO) 본 발명은 도전성 패드가 형성된 소자를 준비하는 단계; 상기 도전성 패드 및 상기 소자의 적어도 일부 상에 절연층을 형성하는 단계; 상기 절연층을 식각하여 상기 도전성 패드를 노출시키는 캐비티를 구비하는 절연층 패턴을 형성하는 단계; 상기 도전성 패드 및 상기 절연층 패턴 상의 전면에 솔더층을 형성하는 단계; 상기 솔더층에 플라즈마에 의한 디웨팅(dewetting) 처리를 하여 상기 절연층 패턴에 둘러싸인 상기 도전성 패드와 직접 접촉하는 솔더 범프를 형성하는 단계; 및 상기 절연층 패턴을 제거하는 단계;를 포함하는, 솔더 범프 구조체의 제조방법 및 상기 제조방법에 의해 구현되는, 솔더 범프 구조체를 제공한다.
Related patent documents
KR1015421610000*
Latest bibliographic data on file with the International Bureau
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