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1. (WO2015126998) INTERCONNECT ASSEMBLIES WITH THROUGH-SILICON VIAS AND STRESS-RELIEF FEATURES
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2015/126998    International Application No.:    PCT/US2015/016480
Publication Date: 27.08.2015 International Filing Date: 19.02.2015
IPC:
H01L 21/60 (2006.01)
Applicants: MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, P.o. Box 6 Boise, ID 83707-0006 (US)
Inventors: LI, Hongqi; (US).
JINDAL, Anurag; (US).
LU, Jin; (US).
DAMARLA, Gowrisankar; (US).
RAMALINGAM, Shyam; (US)
Agent: KLASSEN, Karl, L.; (US)
Priority Data:
14/188,367 24.02.2014 US
Title (EN) INTERCONNECT ASSEMBLIES WITH THROUGH-SILICON VIAS AND STRESS-RELIEF FEATURES
(FR) ENSEMBLES D'INTERCONNEXION À TROUS D'INTERCONNEXION DANS LE SILICIUM ET À ÉLÉMENTS DE RELAXATION DES CONTRAINTES
Abstract: front page image
(EN)A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress- relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.
(FR)Un dispositif à semi-conducteur selon certains modes de réalisation de l'invention comprend une structure de substrat et une interconnexion conductrice s'étendant à travers au moins une partie de la structure de substrat. L'interconnexion conductrice peut comprendre un trou d'interconnexion dans le silicium et un élément de relaxation des contraintes qui permet la dilatation thermique et/ou la contraction thermique du matériau afin de gérer des contraintes internes dans le dispositif à semi-conducteur. Des procédés de fabrication du dispositif à semi-conducteur selon certains modes de réalisation consistent à retirer de la matière de l'interconnexion conductrice pour former l'espace de relaxation des contraintes.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)