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1. (WO2015125685) ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING SAME
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/125685 International Application No.: PCT/JP2015/053808
Publication Date: 27.08.2015 International Filing Date: 12.02.2015
IPC:
G02F 1/1368 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/786 (2006.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
岡田 訓明 OKADA Kuniaki; null
内田 誠一 UCHIDA Seiichi; null
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2014-03173821.02.2014JP
Title (EN) ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING SAME
(FR) SUBSTRAT DE MATRICE ACTIVE ET SON PROCÉDÉ DE PRODUCTION
(JA) アクティブマトリクス基板およびその製造方法
Abstract:
(EN) Each pixel region (P) of an active matrix substrate (101) is provided with: a thin film transistor (10); an interlayer insulating layer (11) containing an organic insulating layer; a transparent connection layer (13a) formed on the interlayer insulating layer (11); an inorganic insulating layer (15) formed on the transparent connection layer (13a); and a pixel electrode (19) formed on the inorganic insulating layer (15). The transparent connection layer (13a) is in contact with a drain electrode within a first contact hole (CH1) that is provided in the interlayer insulating layer (11), and the pixel electrode (19) is in contact with the transparent connection layer (13a) within a second contact hole (CH2) that is provided in the inorganic insulating layer (15). The first contact hole and the second contact hole do not overlap each other when viewed from the normal direction of a substrate (1). The bottom surface and the wall surface of the first contact hole are covered by the transparent connection layer (13a), the inorganic insulating layer (15) and the pixel electrode (19) within the first contact hole.
(FR) Selon la présente invention, chaque région de pixel (P) d'un substrat à matrice active (101) est pourvue de : un transistor à couche mince (10); une couche isolante intercouche (11) contenant une couche isolante organique; une couche de connexion transparente (13a) formée sur la couche isolante intercouche (11); une couche isolante inorganique (15) formée sur la couche de connexion transparente (13a); et une électrode de pixel (19) formée sur la couche isolante inorganique (15). La couche de connexion transparente (13a) est en contact avec une électrode de drain à l'intérieur d'un premier trou de contact (CH1) qui est disposé dans la couche isolante intercouche (11), et l'électrode de pixel (19) est en contact avec la couche de connexion transparente (13a) à l'intérieur d'un deuxième trou de contact (CH2) qui est disposé dans la couche isolante inorganique (15). Le premier trou de contact et le deuxième trou de contact ne se chevauchent pas mutuellement en observant depuis la direction normale par rapport à un substrat (1). La surface inférieure et la surface de paroi du premier trou de contact sont recouvertes par la couche de connexion transparente (13a), la couche isolante inorganique (15) et l'électrode de pixel (19) à l'intérieur du premier trou de contact.
(JA)  アクティブマトリクス基板(101)における各画素領域(P)は、薄膜トランジスタ(10)と、有機絶縁層を含む層間絶縁層(11)と、層間絶縁層(11)上に形成された透明接続層(13a)と、透明接続層(13a)上に形成された無機絶縁層(15)と、無機絶縁層(15)上に形成された画素電極(19)とを備え、透明接続層(13a)は、層間絶縁層(11)に設けられた第1のコンタクトホール(CH1)内でドレイン電極と接し、画素電極(19)は、無機絶縁層(15)に設けられた第2のコンタクトホール(CH2)内で透明接続層(13a)と接しており、基板(1)の法線方向から見たとき、第1のコンタクトホールと、第2のコンタクトホールとは互いに重なっておらず、第1のコンタクトホール内において、第1のコンタクトホールの底面および壁面は、透明接続層(13a)、無機絶縁層(15)および画素電極(19)で覆われている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)