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1. (WO2015123913) METHOD FOR MANUFACTURING LOW-TEMPERATURE POLYCRYSTALLINE SILICON THIN-FILM TRANSISTOR AND ARRAY SUBSTRATE

Pub. No.:    WO/2015/123913    International Application No.:    PCT/CN2014/074421
Publication Date: Fri Aug 28 01:59:59 CEST 2015 International Filing Date: Tue Apr 01 01:59:59 CEST 2014
IPC: H01L 21/336
H01L 29/786
Applicants: BOE TECHNOLOGY GROUP CO., LTD.
京东方科技集团股份有限公司
Inventors: MAO, Xue
毛雪
Title: METHOD FOR MANUFACTURING LOW-TEMPERATURE POLYCRYSTALLINE SILICON THIN-FILM TRANSISTOR AND ARRAY SUBSTRATE
Abstract:
A method for manufacturing a low-temperature polycrystalline silicon thin-film transistor and an array substrate, which is used to simplify the manufacturing process flow of a thin-film transistor. The method for manufacturing a low-temperature polycrystalline silicon thin-film transistor comprises the steps of: forming a non-crystalline silicon layer (12) on a substrate (1); forming an impurity film layer (13) on the non-crystalline silicon layer (12), the position of the impurity film layer (13) respectively corresponding to a source electrode doping layer (140) to be formed and a drain electrode doping layer (150) to be formed; and converting the non-crystalline silicon layer (12) into a polycrystalline silicon layer (29), and in the process of converting the non-crystalline silicon layer (12) into the polycrystalline silicon layer (29), implanting ions in the impurity film layer (13) into the area where the polycrystalline silicon layer (29) comes into contact with the impurity film layer (13), so as to form the source electrode doping layer (140) and the drain electrode doping layer (150). More specifically, an excimer laser annealing process is executed on the non-crystalline silicon layer (12) and the impurity film layer (13), so that the source electrode doping layer (140) is formed in the area corresponding to the source electrode doping layer (140) to be formed, and the drain electrode doping layer (150) is formed in the area corresponding to the drain electrode doping layer (150) to be formed; and the area, except for the source electrode doping layer (140) and the drain electrode doping layer (150), is the polycrystalline silicon layer (29).