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1. (WO2015119709) VERTICAL POWER MOSFET INCLUDING PLANAR CHANNEL
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/119709 International Application No.: PCT/US2014/068857
Publication Date: 13.08.2015 International Filing Date: 05.12.2014
IPC:
H01L 29/78 (2006.01) ,H01L 29/732 (2006.01) ,H01L 21/8224 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
73
Bipolar junction transistors
732
Vertical transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8222
Bipolar technology
8224
comprising a combination of vertical and lateral transistors
Applicants: MAXPOWER SEMICONDUCTOR, INC.[US/US]; 181 Metro Drive Suite 590 San Jose, California 95110, US
Inventors: ZENG, Jun; US
DARWISH, Mohamed N.; US
PU, Kui; CN
SU, Shih-Tzung; CN
Agent: OGONOWSKY, Brian D.; US
Priority Data:
14/338,30322.07.2014US
61/935,70704.02.2014US
Title (EN) VERTICAL POWER MOSFET INCLUDING PLANAR CHANNEL
(FR) TRANSISTOR MOS À PUISSANCE VERTICALE COMPRENANT UN CANAL PLAN
Abstract:
(EN) A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. Alternating N and P-type columns are formed over the drift layer with a higher dopant concentration. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and next to the sidewalls as a vertical field plate. A source electrode contacts the P-well and source region. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls. Current between the source and drain flows laterally and then vertically through the various N layers. On resistance is reduced and the breakdown voltage is increased.
(FR) L'invention concerne une cellule de transistor MOS de puissance comportant un substrat de silicium N+ possédant une électrode de drain. Une couche de dérive de type N à faible concentration de dopant est développée sur le substrat. Des colonnes de type P et de type N en alternance sont formées sur la couche de dérive et possèdent une concentration de dopant plus importante. Une couche de type N, possédant une concentration de dopant plus importante que la région de dérive, est ensuite formée et gravée afin d'avoir des parois latérales. Un puits P est formé sur la couche de type N, et une région source N+ est formée dans le puits P. Une grille est formée sur le canal latéral du puits P et à côté des parois latérales comme une plaque de champ vertical. Une électrode source est en contact avec le puits P et la région source. Une tension de grille positive inverse le canal latéral et augmente la conduction le long des parois latérales. Le courant entre la source et le drain circule latéralement puis verticalement dans les diverses couches N. La résistance à l'état passant est réduite et la tension de claquage est augmentée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)