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Machine translation
1. (WO2015116749) METHODS AND APPARATUS FOR PROVIDING AN INTERPOSER FOR INTERCONNECTING SEMICONDUCTOR CHIPS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/116749 International Application No.: PCT/US2015/013405
Publication Date: 06.08.2015 International Filing Date: 29.01.2015
IPC:
H01L 23/15 (2006.01) ,H01L 23/498 (2006.01)
Applicants: CORNING INCORPORATED[US/US]; 1 Riverfront Plaza Corning, New York 14831, US
Inventors: CHAPARALA, Satish Chandra; US
POLLARD, Scott Christopher; US
Agent: HARAN, John T; US
Priority Data:
61/934,36631.01.2014US
Title (EN) METHODS AND APPARATUS FOR PROVIDING AN INTERPOSER FOR INTERCONNECTING SEMICONDUCTOR CHIPS
(FR) PROCÉDÉS ET APPAREIL DE FOURNITURE D'UN INTERPOSEUR D'INTERCONNEXION DE PUCES SEMI-CONDUCTRICES
Abstract: front page image
(EN) Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate.
(FR) La présente invention concerne des procédés et un appareil de fourniture d'un interposeur d'interconnexion d'une ou de plusieurs puces semi-conductrices avec un substrat organique dans un boîtier semi-conducteur, l'interposeur comprenant : un premier substrat en verre comportant des première et seconde surfaces principales opposées, le premier substrat en verre ayant un premier coefficient de dilatation thermique (CTE1) ; un second substrat en verre comportant des première et seconde surfaces principales opposées, le second substrat en verre ayant un second coefficient de dilatation thermique (CTE2) ; et une interface disposée entre les premier et second substrats en verre et reliant la seconde surface principale du premier substrat en verre à la première surface principale du second substrat en verre, le CTE1 étant inférieur au CTE2, la première surface principale du premier substrat en verre fonctionnant de sorte à venir en contact avec la ou les puces semi-conductrices, et la seconde surface principale du second substrat en verre fonctionnant de sorte à venir en contact avec le substrat organique.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)