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1. (WO2015115002) FINE PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING DEVICE, AND RECORDING MEDIUM
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/115002 International Application No.: PCT/JP2014/084087
Publication Date: 06.08.2015 International Filing Date: 24.12.2014
IPC:
H01L 21/3065 (2006.01) ,H01L 21/302 (2006.01) ,H01L 21/336 (2006.01) ,H01L 21/8247 (2006.01) ,H01L 27/115 (2006.01) ,H01L 29/788 (2006.01) ,H01L 29/792 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8239
Memory structures
8246
Read-only memory structures (ROM)
8247
electrically-programmable (EPROM)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
788
with floating gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
792
with charge trapping gate insulator, e.g. MNOS-memory transistor
Applicants: HITACHI KOKUSAI ELECTRIC INC.[JP/JP]; 14-1, Sotokanda 4-chome, Chiyoda-ku, Tokyo 1018980, JP
Inventors: SHIMAMOTO, Satoshi; JP
YUGAMI, Jiro; JP
HIROSE, Yoshiro; JP
KIKUCHI, Toshiyuki; JP
Priority Data:
2014-01428129.01.2014JP
Title (EN) FINE PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING DEVICE, AND RECORDING MEDIUM
(FR) PROCÉDÉ DE FORMATION DE MOTIF FIN, PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR, DISPOSITIF DE TRAITEMENT DE SUBSTRAT ET SUPPORT D'ENREGISTREMENT
(JA) 微細パターンの形成方法、半導体装置の製造方法、基板処理装置及び記録媒体
Abstract:
(EN) In order to provide a technique for highly selectively etching a first film mainly consisting of silicon with respect to a second film having a lower silicon content than the first film, a fine pattern forming method includes: a step of forming a first fine pattern by forming a stacked film including the first film mainly consisting of silicon and the second film having a lower silicon content than the first film, and providing a plurality of first holes in the formed stacked film; a step of forming a second fine pattern by forming channels in the respective plurality of first holes and then providing second holes between the respective channels; and an etching step of removing the first film adjacent to the second holes by supplying an etching gas containing fluorine to the second fine pattern. In the etching step, the first film is removed until the etching gas reaches the film forming the channels formed of the same type of film as the second film.
(FR) L'invention concerne, afin de fournir une technique de gravure hautement sélective d'un premier film consistant principalement en du silicium par rapport à un second film ayant une teneur en silicium plus basse que le premier film, un procédé de formation de motif fin comprenant : une étape de formation d'un premier motif fin en formant un film empilé incluant le premier film consistant principalement en du silicium et le second film ayant une teneur en silicium plus basse que le premier film, et de fourniture d'une pluralité de premiers trous dans le film empilé formé ; une étape de formation d'un deuxième motif fin en formant des canaux dans la pluralité respective de premiers trous, puis la fourniture de seconds trous entre les canaux respectifs ; et une étape de gravure d'élimination du premier film adjacent aux seconds trous par une alimentation en gaz de gravure contenant du fluor du deuxième motif fin. Dans l'étape de gravure, le premier film est éliminé jusqu'à ce que le gaz de gravure atteigne le film formant les canaux formés du même type de film que le second film.
(JA) シリコンを主成分とする第1の膜に対して、前記第1の膜よりもシリコン含有率が少ない膜である第2の膜に対して、高選択にエッチングする技術を提供するために、シリコンを主成分とする第1の膜と前記第1の膜よりもシリコン含有率が少ない第2の膜を含む積層膜を形成し、形成された積層膜に複数の第一穴を設けて第1微細パターンを形成する工程と、前記複数の第一穴夫々にチャネルを形成した後、前記夫々のチャネル間に第二穴を設けて第2微細パターンを形成する工程と、前記第2微細パターンにフッ素を含むエッチングガスを供給して、前記第二穴に隣接された前記第1の膜を除去するエッチング工程と、を有し、前記エッチング工程では、前記第2の膜と同じ膜種で形成された前記チャネルを形成する膜に前記エッチングガスが到達するまで前記第1の膜を除去するように構成する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)