WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2015114698) TRANSISTOR PACKAGE, AMPLIFIER CIRCUIT CONTAINING SAME, AND TRANSISTOR DESIGN METHOD
Latest bibliographic data on file with the International Bureau   

Pub. No.:    WO/2015/114698    International Application No.:    PCT/JP2014/005161
Publication Date: 06.08.2015 International Filing Date: 10.10.2014
IPC:
H03F 1/07 (2006.01), H03F 3/213 (2006.01), H03F 3/60 (2006.01), H03F 3/68 (2006.01)
Applicants: NEC CORPORATION [JP/JP]; 7-1, Shiba 5-chome, Minato-ku, Tokyo 1088001 (JP)
Inventors: SHIIKUMA, Kazumi; (JP)
Agent: IEIRI, Takeshi; (JP)
Priority Data:
2014-017171 31.01.2014 JP
Title (EN) TRANSISTOR PACKAGE, AMPLIFIER CIRCUIT CONTAINING SAME, AND TRANSISTOR DESIGN METHOD
(FR) BOITIER DE TRANSISTORS, CIRCUIT D'AMPLIFICATEUR CONTENANT CELUI-CI ET PROCEDE DE CONCEPTION DE TRANSISTOR
(JA) トランジスタパッケージ、それを備えた増幅回路、及び、トランジスタの構成方法
Abstract: front page image
(EN)A transistor package in one embodiment contains main transistors (MT1, MT2) and a sub-transistor (ST1) that is provided in the same package as and is smaller than said main transistors (MT1, MT2). This makes it possible to provide the following: a more versatile transistor package that makes it possible to construct a variety of Doherty amplifier circuits such as a Doherty amplifier circuit with auto-bias functionality added thereto or an extended Doherty amplifier circuit with desired operating characteristics; an amplifier circuit containing said transistor package; and a transistor design method.
(FR)Dans une forme de réalisation, l'invention concerne un boîtier de transistors qui contient des transistors (MT1, MT2) principaux et un sous-transistor (ST1), prévu dans le même boîtier et qui est plus petit que lesdits transistors (MT1, MT2) principaux. L'invention se réfère ainsi : à un boîtier de transistors plus polyvalent qui permet de construire divers circuits d'amplificateur de Doherty, tels qu'un circuit d'amplificateur de Doherty à fonctionnalité d'auto-polarisation ajoutée, ou un circuit d'amplificateur de Doherty étendu possédant des caractéristiques de fonctionnement voulues; à un circuit d'amplificateur contenant ledit boîtier de transistors; et à un procédé de conception de transistor.
(JA) 一実施の形態によれば、トランジスタパッケージは、メイントランジスタ(MT1,MT2)と、メイントランジスタ(MT1,MT2)と同じパッケージ内に設けられ、メイントランジスタ(MT1,MT2)よりもサイズの小さいサブトランジスタ(ST1)と、を備える。それにより、オートバイアス機能が付加されたドハティ増幅回路や、所望の動作特性の拡張型ドハティ増幅回路等、様々な種類のドハティ増幅回路を構成することが可能なより汎用性の高いトランジスタパッケージ、それを備えた増幅回路、及び、トランジスタの構成方法を提供することができる。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)