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1. (WO2015047350) DUAL-SIDED DIE PACKAGES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/047350 International Application No.: PCT/US2013/062471
Publication Date: 02.04.2015 International Filing Date: 27.09.2013
IPC:
H01L 23/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, CA 95052, US
Inventors:
BRAUNISCH, Henning; US
EID, Feras; US
ELSHERBINI, Adel, A.; US
SWAN, Johanna, M.; US
NELSON, Don, W.; US
Agent:
BABBITT, William, Thomas; Blakely Sokoloff Taylor & Zafman LLP 1279 Oakmead Parkway Sunnyvale, CA 94085, US
Priority Data:
Title (EN) DUAL-SIDED DIE PACKAGES
(FR) BOÎTIERS DE PUCE DOUBLE FACE
Abstract:
(EN) An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.
(FR) L'invention concerne un appareil comprenant une puce, un premier côté de la puce comportant un premier type de points de contact de niveau système et un second côté comportant un second type de points de contact ; et un substrat de boîtier couplé à la puce et au second côté de la puce. L'invention concerne également un appareil comprenant une puce, un premier côté de la puce comportant une pluralité de points de contact de logique de niveau système et un second côté comportant une seconde pluralité de points de contact d'alimentation de niveau système. L'invention concerne en outre un procédé consistant à coupler soit un premier type de points de contact de niveau système, sur un premier côté d'une puce, soit un second type de points de contact de niveau système, sur un second côté de la puce, à un substrat de boîtier.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)