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1. (WO2015047341) NON-PLANAR SEMICONDUCTOR DEVICES HAVING MULTI-LAYERED COMPLIANT SUBSTRATES
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2015/047341 International Application No.: PCT/US2013/062445
Publication Date: 02.04.2015 International Filing Date: 27.09.2013
IPC:
H01L 21/336 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard MS: RNB-4-150 Santa Clara, California 95054, US
Inventors:
KAVALIEROS, Jack T.; US
RADOSAVLJEVIC, Marko; US
METZ, Matthew V.; US
THEN, Han Wui; US
CHU-KUNG, Benjamin; US
LE, Van H.; US
MUKHERJEE, Niloy; US
DASGUPTA, Sansaptak; US
PILLARISETTY, Ravi; US
DEWEY, Gilbert; US
CHAU, Robert S.; US
ZELICK, Nancy M.; US
RACHMADY, Willy; US
Agent:
BRASK, Justin K.; Blakely, Sokoloff, Taylor & Zafman LLP 1279 Oakmead Parkway Sunnyvale, California 94085-4040, US
Priority Data:
Title (EN) NON-PLANAR SEMICONDUCTOR DEVICES HAVING MULTI-LAYERED COMPLIANT SUBSTRATES
(FR) DISPOSITIFS À SEMI-CONDUCTEURS NON PLANS COMPORTANT DES SUBSTRATS SOUPLES MULTICOUCHES
Abstract:
(EN) Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a lower portion composed of a first semiconductor material with a first lattice constant (L1), and has an upper portion composed of a second semiconductor material with a second lattice constant (L2). A cladding layer is disposed on the upper portion, but not on the lower portion, of the semiconductor fin. The cladding layer is composed of a third semiconductor material with a third lattice constant (L3), wherein L3 > L2 > L1. A gate stack is disposed on a channel region of the cladding layer. Source/drain regions are disposed on either side of the channel region.
(FR) L'invention porte sur des dispositifs à semi-conducteurs non plans comportant des substrats souples multicouches et sur des procédés de fabrication de tels dispositifs à semi-conducteurs non plans. Par exemple, un dispositif à semi-conducteurs comprend une ailette semi-conductrice disposée au-dessus d'un substrat à semi-conducteurs. L'ailette semi-conductrice comporte une partie inférieure composée d'un premier matériau semi-conducteur présentant une première constante de réseau (L1) et comporte une partie supérieure composée d'un deuxième matériau semi-conducteur présentant une deuxième constante de réseau (L2). Une couche de revêtement est disposée sur la partie supérieure, mais pas sur la partie inférieure, de l'ailette semi-conductrice. La couche de revêtement est composée d'un troisième matériau semi-conducteur présentant une troisième constante de réseau (L3), L3 > L2 > L1. Un empilement de grilles est disposé sur une région de canal de la couche de revêtement. Des régions de source/drain sont disposées sur l'un ou l'autre côté de la région de canal.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)